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ABCDECompal ConfidentialModel Name : JM40-HR File Name : LA-7231P1 12Compal ConfidentialJM40-HR M/B Schematics DocumentIntel Sandy Bridge Processor with DDRIII + Cougar Point PCH Nvidia N12P-GS/GV-OP233 REV:1.0ZZZPart NumberDescriptionDAZ0IO0_PCB PCB P4LJ0 LA-7231P LS-P/P ZZZPart Number4Description4DC30100DT00 DC_IN_CABLE_90W P4LJ0_DCIN_CABLE_90W 90W@ ZZZPart NumberDescription Security Classification Issued Date DC30100DS00 DC_IN_CABLE_65W P4LJ0_DCIN_CABLE_65W 65W@Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.SCHEMATIC, MB LA-7231PSize Document Number Custom Date:4019BLSheetERev B 1 of 57Friday, March 04, 2011ABCDABCDEP4LJ0 Block Diagram1Fan Controlpage 381PEG(DIS) VRAM * 8 DDR364*16 128*16100MHzPCI-E 2.0x16 5GT/s PER LANE 133MHzNvidia N12P-GS/GV 973pin BGApage22~30 (reserved) page 32Intel Sandy BridgeProcessor DC/QC 35W SV rPGA989Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Dual ChannelBANK 0, 1, 2, 3page 11,12 1.5V DDRIII EDPHDMI(Reserved Only) HDMI Conn.page 332page 4~10FDI x8 CRT Conn. LVDS Conn.page 32 page 31 100MHz 2.7GT/sDMI x4100MHz 1GB/s x4USB 2.0 conn x2USB port 0,1 on USB/B page 37Bluetooth ConnUSB port 13 page 37CMOS CameraUSB port 10 page 31Mini Card (WWAN,SIM)USB port 9,12 on 3G/B page 372HDMI(UMA/Optimus)LVDS(UMA/Optimus) CRT(UMA/Optimus) TMDS(UMA/Optimus)PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)100MHzIntel Cougar Point-MPCH 989pin BGApage 13~21USBx14 HD Audio3.3V 48MHz3.3V 24MHzHDA CodecCX20584port 4port 3WLANport 2port 1USB 3.0 controller UPD + Charger page 46SATA x 6 100MHz (GEN1 1.5GT/S ,GEN2 3GT/S)SPIpage 43MINI Card x1USB port 8 page 37LAN(GbE)AR8151page 35SPI ROM x1port 0 port 2page 143USB 3.0 conn x1page 46Card Reader RTS5209page 38RJ45page 36SATA HDD Conn.SATA CDROM Conn.page 34page 34LPC BUS33MHzInt. Speakerpage 43DMICpage 43MIC Jackon USB/B page 37HP/SPDIF Jack on USB/Bpage 373Sub-board LS-7231P RTC CKT.page 13ENE KB930LS-7237PDoor/Bpage 40 page 39Power/Bpage 41Touch Padpage 40Int.KBDpage 40Power On/Off CKT.page 40LS-PUSB_Auido/B USB Port0,1 page 37BIOS ROMpage 394DC/DC Interface CKT.4LS-7233PFUN/Bpage 41page 45Power Circuit DC/DCpage 47~55LS-7234P3G USB Port9,12 page 37Security Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc. SCHEMATIC, MB LA-7231PSize Document Number Custom Rev B SheetETHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C D4019BLDate:Friday, March 04, 20112of57ABCDEVoltage RailsPower Plane VIN BATT+ B+1STATEDescription Adapter power supply (19V) Battery power supply (12.6V) AC or battery power rail for power circuit. Core voltage for CPU Core voltage for GPU Core voltage for UMA graphic +0.75VP to +0.75VS switched power rail for DDR terminator +1.05VSDGPU power rail for GPU +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU +1.05VS_VCCP to +1.05VS_PCH power for PCH +1.5VP to +1.5V power rail for DDRIII +1.5V to +1.5VS switched power rail +1.5VS to +1.5VSDGPU switched power rail for GPU (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU +3VALW always on power rail +3VALW always to KBC +3VALW to +3V_LAN power rail for LAN +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) +3VALW to +3VS power rail +5VALWP to +5VALW power rail +5VALW to +5VALW_PCH power rail for PCH (Short resister) +5VALW to +5VS switched power rail +VSBP to +VSB always on power rail for sequence control RTC power S1 N/A N/A N/A ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON ON S3 N/A N/A N/A OFF OFF OFF OFF OFF OFF OFF ON OFF OFF OFF ON ON ON ON OFF ON ON OFF ON ON S5 N/A N/A N/A OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON* ON* ON* ON* OFF ON* ON* OFF ON* ONSIGNALSLP_S1# SLP_S3# SLP_S4# SLP_S5# HIGH LOW LOW LOW LOW HIGH HIGH LOW LOW LOW HIGH HIGH HIGH LOW LOW HIGH HIGH HIGH HIGH LOW+VALW ON ON ON ON ON+V ON ON ON OFF OFF+VS ON ON OFF OFF OFFClock ON LOW OFF1Full ON S1(Power On Suspend) S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF)+CPU_CORE +VGA_CORE +VGFX_CORE +0.75VS +1.05VSDGPU +1.05VS_VCCP +1.05VS_PCH +1.5V +1.5VS +1.5VSDGPU +1.8VS +3VALW +3VALW_EC +3V_LAN +3VALW_PCH +3VSOFF OFFBoard ID/ Project ID Table for AD channelVcc Ra/Rc/ReBoard ID2+5VALW +5VALW_PCH +5VS +VSB +RTCVCC0 1 2 3 4 5 6 73.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 0 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NCV AD_BID min 0 V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 VV AD_BID typ 0 V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 VV AD_BID max 0 V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V2BOARD ID TableBoard ID 0 1 2 3 4 5 6 7 PCB Revision 0.1 0.2 0.3 1.0BTO Option TableBTO Item UMA Only N12P-GS N12P-GV Discrete(OPTIMUS) VRAM Blue Tooth AR8151 Connector Unpop BOM Structure UMAO@ GS@ GV@ OPT@ X76@ BT@ 8151@ CONN@ @3Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.EC SM Bus1 addressDeviceSmart BatteryEC SM Bus2 addressDevice AddressAddressX bPCH SM Bus address3DeviceClock Generator (9LVS3199AKLFT, RTM890N-631-VB-GRT) DDR DIMM0 DDR DIMM2Addressb Xb XbProject ID TableProject ID 0 1 2 3 4 5 6 7 Project Name P3LJ0 P4LJ0 P5LJ0 P3LS0 P4LS0 P5LS0USB Port TableUSB 2.0 USB 1.1 Port UHCI0 UHCI1 EHCI1 UHCI2 UHCI3 UHCI4 EHCI2 UHCI5 UHCI6 0 1 2 3 4 5 6 7 8 9 10 11 12 13 3 External USB Port USB/B (Right Side) USB/B (Right Side)Mini Card(WLAN) Mini Card(WWAN) Camera SIM Card Blue Tooth44Security Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc. SCHEMATIC, MB LA-7231PSize Document Number Custom Rev B SheetETHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.A B C D4019BLDate:Friday, March 04, 20113of5754321D+1.05VS_VCCP 1R1 24.9_0402_1% PEG_COMP 2 JCPU1A PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] J22 J21 H22 K33 M35 L34 J35 J32 H34 H31 G33 G30 F35 E34 E32 D33 D31 B33 C32 J33 L35 K34 H35 H32 G34 G31 F33 F30 E35 E33 F32 D34 E31 C33 B32 M29 M32 M31 L32 L29 K31 K28 J30 J28 H29 G27 E29 F27 D28 F26 E25 M28 M33 M30 L31 L28 K30 K27 J29 J27 H28 G28 E28 F28 D27 E26 D25PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils - typical impedance = 14.5 mohmsD15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3B27 B25 A25 B24 B28 B26 A24 B23 G21 E22 F21 D21 G22 D22 F20 C21DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3]PCI EXPRESS* - GRAPHICSCPEG_GTX_C_HRX_N15 PEG_GTX_C_HRX_N14 PEG_GTX_C_HRX_N13 PEG_GTX_C_HRX_N12 PEG_GTX_C_HRX_N11 PEG_GTX_C_HRX_N10 PEG_GTX_C_HRX_N9 PEG_GTX_C_HRX_N8 PEG_GTX_C_HRX_N7 PEG_GTX_C_HRX_N6 PEG_GTX_C_HRX_N5 PEG_GTX_C_HRX_N4 PEG_GTX_C_HRX_N3 PEG_GTX_C_HRX_N2 PEG_GTX_C_HRX_N1 PEG_GTX_C_HRX_N0 PEG_GTX_C_HRX_P15 PEG_GTX_C_HRX_P14 PEG_GTX_C_HRX_P13 PEG_GTX_C_HRX_P12 PEG_GTX_C_HRX_P11 PEG_GTX_C_HRX_P10 PEG_GTX_C_HRX_P9 PEG_GTX_C_HRX_P8 PEG_GTX_C_HRX_P7 PEG_GTX_C_HRX_P6 PEG_GTX_C_HRX_P5 PEG_GTX_C_HRX_P4 PEG_GTX_C_HRX_P3 PEG_GTX_C_HRX_P2 PEG_GTX_C_HRX_P1 PEG_GTX_C_HRX_P0 PEG_HTX_GRX_N15 PEG_HTX_GRX_N14 PEG_HTX_GRX_N13 PEG_HTX_GRX_N12 PEG_HTX_GRX_N11 PEG_HTX_GRX_N10 PEG_HTX_GRX_N9 PEG_HTX_GRX_N8 PEG_HTX_GRX_N7 PEG_HTX_GRX_N6 PEG_HTX_GRX_N5 PEG_HTX_GRX_N4 PEG_HTX_GRX_N3 PEG_HTX_GRX_N2 PEG_HTX_GRX_N1 PEG_HTX_GRX_N0 PEG_HTX_GRX_P15 PEG_HTX_GRX_P14 PEG_HTX_GRX_P13 PEG_HTX_GRX_P12 PEG_HTX_GRX_P11 PEG_HTX_GRX_P10 PEG_HTX_GRX_P9 PEG_HTX_GRX_P8 PEG_HTX_GRX_P7 PEG_HTX_GRX_P6 PEG_HTX_GRX_P5 PEG_HTX_GRX_P4 PEG_HTX_GRX_P3 PEG_HTX_GRX_P2 PEG_HTX_GRX_P1 PEG_HTX_GRX_P0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K OPT@ 0.1U_K PEG_HTX_C_GRX_N15 PEG_HTX_C_GRX_N14 PEG_HTX_C_GRX_N13 PEG_HTX_C_GRX_N12 PEG_HTX_C_GRX_N11 PEG_HTX_C_GRX_N10 PEG_HTX_C_GRX_N9 PEG_HTX_C_GRX_N8 PEG_HTX_C_GRX_N7 PEG_HTX_C_GRX_N6 PEG_HTX_C_GRX_N5 PEG_HTX_C_GRX_N4 PEG_HTX_C_GRX_N3 PEG_HTX_C_GRX_N2 PEG_HTX_C_GRX_N1 PEG_HTX_C_GRX_N0 PEG_HTX_C_GRX_P15 PEG_HTX_C_GRX_P14 PEG_HTX_C_GRX_P13 PEG_HTX_C_GRX_P12 PEG_HTX_C_GRX_P11 PEG_HTX_C_GRX_P10 PEG_HTX_C_GRX_P9 PEG_HTX_C_GRX_P8 PEG_HTX_C_GRX_P7 PEG_HTX_C_GRX_P6 PEG_HTX_C_GRX_P5 PEG_HTX_C_GRX_P4 PEG_HTX_C_GRX_P3 PEG_HTX_C_GRX_P2 PEG_HTX_C_GRX_P1 PEG_HTX_C_GRX_P0DMIPEG_GTX_C_HRX_N[0..15] 22 PEG_GTX_C_HRX_P[0..15] 22 PEG_HTX_C_GRX_N[0..15] 22 PEG_HTX_C_GRX_P[0..15] 22C15 15 15 15 15 15 15 15 +1.05VS_VCCPFDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7A22 G19 E20 G18 B20 C19 D19 F17 J18 J17 H20 J19 H17FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC15 FDI_FSYNC0 15 FDI_FSYNC1 15 FDI_INTBeDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance &25 mohms1R2 24.9_15 FDI_LSYNC0 15 FDI_LSYNC1Intel(R) FDI15 15 15 15 15 15 15 15FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7A21 H19 E19 F18 B21 C20 D18 E17FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3]BEDP_COMP 31 31 31 EDP_HPD# EDP_AUXP EDP_AUXNA18 A17 B16 C15 D15 C17 F16 C16 G15 C18 E16 D16 F15eDP_COMPIO eDP_ICOMPO eDP_HPD eDP_AUX eDP_AUX# eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] SUYIN_8_SANDY BRIDGE31 31EDP_TXP0 EDP_TXP131 31EDP_TXN0 EDP_TXN1CONN@eDPTyp- suggest 220nF. The change in AC capacitor value from 100nF to 220nF is to enable compatibility with future platforms having PCIE Gen3 (8GT/s)AASecurity Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet1THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Size Document Number Custom Date: Friday, March 04, 2011 4 of 57543254321DDFor eDPCLK_CPU_DPLL_R CLK_CPU_DPLL#_R R25 R26 1 EDP@ 1 EDP@ 2 0_ 0_0402_5% CLK_CPU_DPLL 14 CLK_CPU_DPLL# 14JCPU1BCIf support EDP 1. Mount R25, R26 2. Remove R30, R31CMISC17 H_SNB_IVB#PROC_SELECT# SKTOCC#+1.05VS_VCCPAN34CLOCKSC26BCLK BCLK#A28 A27CLK_CPU_DMI CLK_CPU_DMI#CLK_CPU_DMI 14 CLK_CPU_DMI# 14Processor Pullups2 1 62_0402_5% H_PROCHOT# T5 PAD @ H_CATERR# AL33DPLL_REF_CLK DPLL_REF_CLK#A16 A15CLK_CPU_DPLL_R CLK_CPU_DPLL#_RR30 R311 LVDS@ 2 1K_ LVDS@ 2 1K_0402_5%+1.05VS_VCCPR28CATERR#18,39 R34 2 1 10K_0402_5% H_CPUPWRGD_RH_PECIH_PECI_ISOTHERMALR32 0_ 2 R36 56_ 2 R38 0_ 2AN33PECISM_DRAMRST#R8H_DRAMRST#H_DRAMRST# 639,50 H_PROCHOT#H_PROCHOT#_RDDR3 MISCAL32PROCHOT#SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]AK1 A5 A4SM_RCOMP0 SM_RCOMP1 SM_RCOMP2R33 R35 R372 2 21 140_ 25.5_ 200_0402_1%18 H_THRMTRIP#H_THEMTRIP#_RAN32THERMTRIP#PU/PD for JTAG signalsXDP_TMS PRDY# PREQ# AP29 AP27 AR26 AR27 AP30 AR28 AP26 XDP_TCK XDP_TMS XDP_TRST# XDP_TDI_R XDP_TDO 2 +3VS R39 2 2 2 2 2 @ @ @ @ @+1.05VS_VCCP+3VSBuffered reset to CPU1 51_ 51_ 51_ 51_ 51_0402_5%BXDP_TDI_R R40 XDP_TDO R41 R43+1.05VS_VCCP 1BPWR MANAGEMENT15 H_PM_SYNC R44 75_0402_5% R49 43_ 2 BUF_CPU_RST# 1 @ R52 0_ 18 H_CPUPWRGD1252U1 Y 4 BUFO_CPU_RST#R48 0_ 21H_PM_SYNC_RJTAG & BPMC35 0.1U_ZR42 0_ 2AM34PM_SYNCTCK TMS TRST# TDI TDOXDP_TCK R17 1K_0402_5%XDP_TRST# R46H_CPUPWRGD_RAP33UNCOREPWRGOOD1 PLT_RST# 2NC AGSN74LVC1G07DCKR_SC70-5R51 130_0402_5% PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_RPV8DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]AL35 AT28 AR29 AR30 AT30 AP32 AR31 AT31 AR32DBRESET#_R1 R502 0_0402_5%XDP_DBRESET#XDP_DBRESET# 15SM_DRAMPWROK3PLT_RST# 17,35,38,39,44BUF_CPU_RST#AR33RESET#Follow DG 0.71+3VS C36 0.1U_Z 1+3VALW +1.5V_CPU_VDDQ 1 SUYIN_8_SANDY BRIDGECONN@2AR62 10K_ 2 15 PM_DRAM_PWRGD C215 1U_V6K @ 15U2 74AHC1G09GW_TSSOP5 2 PM_SYS_PWRGD_BUF 1R61 200_0402_5%1 2B APO 3 G4A2 1 2 DR63 39_0402_5% @ Q2 2N7002E_SOT23-3 @Security Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet146,53SUSPSUSP2 G 3 STHIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.4 3 2Size Document Number Custom Date: Friday, March 04, 2011 5 of 57554321JCPU1CJCPU1D11 DDR_A_D[0..63] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]SA_CLK[0] SA_CLK#[0] SA_CKE[0]AB6 AA6 V9M_CLK_DDR0 11 M_CLK_DDR#0 11 DDR_CKE0_DIMMA 1112 DDR_B_D[0..63] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]SB_CLK[0] SB_CLK#[0] SB_CKE[0]AE2 AD2 R9M_CLK_DDR2 12 M_CLK_DDR#2 12 DDR_CKE2_DIMMB 12DSA_CLK[1] SA_CLK#[1] SA_CKE[1]AA5 AB5 V10M_CLK_DDR1 11 M_CLK_DDR#1 11 DDR_CKE1_DIMMA 11SB_CLK[1] SB_CLK#[1] SB_CKE[1]AE1 AD1 R10M_CLK_DDR3 12 M_CLK_DDR#3 12 DDR_CKE3_DIMMB 12DRSVD_TP[1] RSVD_TP[2] RSVD_TP[3]AB4 AA4 W9RSVD_TP[11] RSVD_TP[12] RSVD_TP[13]AB2 AA2 T9RSVD_TP[4] RSVD_TP[5] RSVD_TP[6]AB3 AA3 W10RSVD_TP[14] RSVD_TP[15] RSVD_TP[16]AA1 AB1 T10SA_CS#[0] SA_CS#[1] RSVD_TP[7] RSVD_TP[8]AK3 AL3 AG1 AH1DDR_CS0_DIMMA# 11 DDR_CS1_DIMMA# 11SB_CS#[0] SB_CS#[1] RSVD_TP[17] RSVD_TP[18]AD3 AE3 AD6 AE6DDR_CS2_DIMMB# 12 DDR_CS3_DIMMB# 12DDR SYSTEM MEMORY ACSA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]C4 G6 J3 M6 AL6 AM8 AR12 AM15DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7DDR_A_DQS#[0..7]11DDR SYSTEM MEMORY BSA_ODT[0] SA_ODT[1] RSVD_TP[9] RSVD_TP[10]AH3 AG3 AG2 AH2M_ODT0 11 M_ODT1 11SB_ODT[0] SB_ODT[1] RSVD_TP[19] RSVD_TP[20]AE4 AD4 AD5 AE5M_ODT2 12 M_ODT3 12SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7]D7 F3 K6 N3 AN5 AP9 AK12 AP15DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7DDR_B_DQS#[0..7]12CSA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]D4 F6 K3 N6 AL5 AM9 AR11 AM14DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7DDR_A_DQS[0..7]11SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7]C7 G3 J6 M3 AN6 AP8 AK11 AP14DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7DDR_B_DQS[0..7]12B11 DDR_A_BS0 11 DDR_A_BS1 11 DDR_A_BS2AE10 AF10 V6SA_BS[0] SA_BS[1] SA_BS[2]11 DDR_A_CAS# 11 DDR_A_RAS# 11 DDR_A_WE#AE8 AD9 AF9SA_CAS# SA_RAS# SA_WE#SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15DDR_A_MA[0..15]1112 DDR_B_BS0 12 DDR_B_BS1 12 DDR_B_BS2AA9 AA7 R6SB_BS[0] SB_BS[1] SB_BS[2]12 DDR_B_CAS# 12 DDR_B_RAS# 12 DDR_B_WE#AA10 AB8 AB9SB_CAS# SB_RAS# SB_WE#SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15DDR_B_MA[0..15]12BSUYIN_8_SANDY BRIDGE +1.5V @ R64 0_ 2 1CONN@SUYIN_8_SANDY BRIDGECONN@R65 1K_0402_5% R66 1K_ 2SD5 H_DRAMRST#H_DRAMRST# R67 4.99K_3DDR3_DRAMRST#_R 1 Q3 BSS138_NL_SOT23-31DDR3_DRAMRST# 11,12A12GA11,12,14 DRAMRST_CNTRL_PCHDRAMRST_CNTRL_PCHC37 0.047U_KSecurity Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet121THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Size Document Number Custom Date: Friday, March 04, 2011 6 of 57543254321CFG Straps for ProcessorCFG2 1 R69 1K_0402_1%D2DJCPU1EPEG Static Lane Reversal - CFG2 is for the 16xRSVD28 RSVD29 RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 L7 AG7 AE7 AK2 W8 AT26 AM33 AJ27CFG2CFG2 CFG4 CFG5 CFG6 CFG7AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN291: Normal O Lane # socket pin map definitiondefinition matchesCFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17]*0:Lane ReversedCFG4 1RSVD37 RSVD38 RSVD39 RSVD40T8 J16 H16 G16Display Port Presence StrapRSVD41 RSVD42 RSVD43 RSVD44 RSVD45 AR35 AT34 AT33 AP35 AR34C2R70 1K_0402_1% EDP@AJ31 AH31 AJ33 AH33change change change changeto to to toVAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSET6 T7 T8 T9PAD PAD PAD PAD@ @ @ @AJ31 AH31 AJ33 AH33 AJ26VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_VAL_SENSE VSS_VAL_SENSE RSVD5CFG41 : D No Physical Display Port attached to Embedded Display PortC*0 : E An external Display Port device is connected to the Embedded Display PortRESERVEDRSVD6 and RSVD7 had changed to SA_DIMM_VREFDQ and SB_DIMMVREFDQ11 SA_DIMM_VREFDQ 12 SB_DIMM_VREFDQ SA_DIMM_VREFDQ SB_DIMM_VREFDQ 1 1 B4 D1RSVD6 RSVD7SA_DIMM_VREFDQ SB_DIMM_VREFDQ For Future CPU M3 support, Sandey bridge not supportM3, Check list1.0&CRB say can NCRSVD46 RSVD47 RSVD48 RSVD49 RSVD50B34 A33 A34 B35 C35CFG6 CFG5 1 R73 1K_0402_1% @ 2 2 1 R74 1K_0402_1% @R71 1K_ 2R72 1K_0402_1%+3VS 1B1 2R75 10K_0402_5% @ VCCIO_SEL VCCIO_SEL R76 10K_0402_5% @F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 J20 B18 A19 J15RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 VCCIO_SEL RSVD27RSVD51 RSVD52AJ32 AK32VCC_DIE_SENSEAH27PADT10PCIE Port Bifurcation StrapsRSVD54 RSVD55 AN35 AM35CFG[6:5]RSVD56 RSVD57 RSVD58 AT2 AT1 AR1*10: x8, x8 - Device 1 function 1 function 211: (Default) x16 - Device 1 functions 1 and 2 disabledBdisabled 01: Reserved - (Device 1 function 1 function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled2KEYB1CFG7 1 R77 1K_0402_1% @VCCIO_SELA19CONN@VCCIO_SELFor 2012 CPU support PEG DEFER TRAININGRSVD26 had changed the name to VCCIO_SEL Need PH +3VS 10K at +1.05VS_VTT source for 2012 processor +1.05V and +1.0V selectCFG7A1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for trainingA2*1/NC : (Default) +1.05VS_VTT 0: +1.0VS_VTTSUYIN_8_SANDY BRIDGESecurity Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet1THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2Size Document Number Custom Date: Friday, March 04, 2011 7 of 5754321SV type CPU+CPU_COREJCPU1FPOWER8.5A+1.05VS_VCCP +1.05VS_VCCP C44 22U_V6M C45 22U_V6M C46 22U_V6M C47 22U_V6M C48 22U_V6M C49 22U_V6M C50 22U_V6M C51 22U_V6M C52 22U_V6M C53 22U_V6M 1 1 1 1 1 1 1 1 1 1 2QC 94A DC 53AAG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 VCCIO40 1 1 1 1 1 C40 10U_V6M C41 10U_V6M C42 10U_V6M C38 10U_V6M C43 10U_V6MD+CPU_COREPEG AND DDRAH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 J2322222222222222D1111111 + 2C58 22U_V6MC59 22U_V6MC62 330U_D2_2V_YC63 330U_D2_2V_YC54 10U_V6MC39 10U_V6MC55 10U_V6MC56 10U_V6MC57 10U_V6MC60 22U_V6MC61 22U_V6M1111@@+ 2222222222Cap quantity follow 43890_HR_CHKLST_Rev0711111111 2 1C65 22U_V6M C73 22U_V6MC66 22U_V6MC67 22U_V6MC68 22U_V6MC69 22U_V6MC70 22U_V6MC71 22U_V6MC72 22U_V6M22222211111112C74 22U_V6MC75 22U_V6MC76 22U_V6MC77 22U_V6MC78 22U_V6MC79 22U_V6MC80 22U_V6MCC2222222CORE SUPPLY+CPU_CORE2+1.05VS_VCCP 1+1.05VS_VCCP 111112SVIDVIDALERT# VIDSCLK VIDSOUTAJ29 AJ30 AJ28H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDATR81 R82R80 43_ 2 1 2 0_ 2 0_0402_5%222222++++1R78 130_0402_5%R79 75_0402_5%C85 330U_D2_2V_YC81 330U_D2_2V_YC82 330U_D2_2V_YC83 330U_D2_2V_YC84 330U_D2_2V_Y+VR_SVID_ALRT# 54 VR_SVID_CLK 54 VR_SVID_DAT 54BPlace the PU resistors close to VRB+CPU_CORE 1Place the PU resistors close to CPUR83 100_0402_1%SENSE LINESVCC_SENSE VSS_SENSEAJ35 VCCSENSE_R AJ34 VSSSENSE_RR84 R851 12 20__0402_5%2VCCSENSE 54 VSSSENSE 54 1VCCIO_SENSE VSSIO_SENSEB10 A10VSSIO_SENSEVCCIO_SENSE 53 VSSIO_SENSE 53 2R86 100_0402_1%AASUYIN_8_SANDY BRIDGECONN@Security Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet1THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2Size Document Number Custom Date: Friday, March 04, 2011 8 of 5754321DD+VGFX_COREQC 33A DC 26AAT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 C95 22U_V6M C89 22U_V6M C90 22U_V6M C96 22U_V6M C91 22U_V6M C92 22U_V6M 1 1 1 1 1 1JCPU1GPOWERSENSE LINESVAXG_SENSE VSSAXG_SENSE AK35 AK34 VCC_AXG_SENSE 54 VSS_AXG_SENSE 54 +1.5V_CPU_VDDQ 1C111+ 2+ 21@@@@@VaxgBSA RAIL? Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed in a common motherboard design, ? VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffedVAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54222222+V_SM_VREF should have 20 mil trace widthSM_VREF AL1 +V_SM_VREF C101 0.1U_Z 1R94 1K_CVREF1 R95 1K_ 2C93 22U_V6MC97 22U_V6MC98 22U_V6MC94 22U_V6MC99 22U_V6MC100 22U_V6M111112222221+1.5V_CPU_VDDQ+1.5VS @ JP2 1 2 PAD-OPEN 4x4mDDR3 -1.5V RAILSVDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1GRAPHICS10A1 1 1 1 1 1 1 + 2 C114 330U_D2_2V_Y C108 10U_V6M C109 10U_V6M C110 10U_V6M C111 10U_V6M C112 10U_V6M C113 10U_V6MC102 330U_D2_2V_YC103 330U_D2_2V_Y11C104 22U_V6MC105 22U_V6MC106 22U_V6MC107 22U_V6M2222222222B6AVCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 M27 M26 L26 J26 J25 J24 H26 H25 +VCCSA C115 10U_V6M C116 10U_V6M C117 10U_V6M C118 10U_V6M @ 1 1 1 1+VCCSAR96 1 + 212 0_0402_5%VCCSA_SENSEC119 330U_D2_2V_Y R97 1 2 0_0402_5% VSSSA_SENSE 52222+1.8VSR98 0_ 2 C120 330U_D2_2V_Y C121 10U_V6M C122 1U_V6K 1 1 11.5A+1.8VS_VCCPLL C123 1U_V6K B6 A6 A2 VCCPLL1 VCCPLL2 VCCPLL31.8V RAIL+ 2MISCVCCSA_SENSEH232VCCSA_SENSE 521FC_C22 VCCSA_VID1222C22 H_FC_C22 C24 2 R99 10K_ 1 R100 0_0402_5% @VCCSA_VID1 52ASUYIN_8_SANDY BRIDGE CONN@A2Security Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet1THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2Size Document Number Custom Date: Friday, March 04, 2011 9 of 5754321JCPU1HDJCPU1I VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2DCBAT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80VSST35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233VSSVSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3CBSUYIN_8_SANDY BRIDGESUYIN_8_SANDY BRIDGECONN@CONN@AASecurity Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet1THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2Size Document Number Custom Date: Friday, March 04, 2011 10 of 5754321+1.5V 1M3 support7 SA_DIMM_VREFDQR102 0_0402_5% @ 1 2 2R101 1K_0402_1%+1.5V JDIMM1 +DIMM0_VREF C124 2.2U_V6K C125 0.1U_Z DDR_A_D0 DDR_A_D1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72+1.5V DDR_A_DQS#[0..7] DDR_A_DQS[0..7] DDR_A_D[0..63] DDR_A_MA[0..15] 6 6 6D6,12,14 DRAMRST_CNTRL_PCHD23 Q8 BSS138_NL_SOT23-3 @1 R103 1K_ 1DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR3_DRAMRST# DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 +1.5V61122111DDR_A_D24 DDR_A_D25222DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 +1.5VDDR_A_D26 DDR_A_D27C6 DDR_CKE0_DIMMA 6 DDR_A_BS2DDR_CKE0_DIMMA DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA16 M_CLK_DDR0 6 M_CLK_DDR#0 6 DDR_A_BS0 6 DDR_A_WE# 6 DDR_A_CAS# 6 DDR_CS1_DIMMA#M_CLK_DDR0 M_CLK_DDR#0 DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMA#DDR_A_D32 DDR_A_D33 DDR_A_DQS#4 DDR_A_DQS4B111222DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 1 1 DDR_A_D62 DDR_A_D63 D_CK_SDATA D_CK_SCLK +0.75VS C207 2 2 C212 2 1 C214For EMI+1.5VDDR_A_D58 DDR_A_D59+3VSAD_CK_SDATA 12,14 D_CK_SCLK 12,140.1U_Z 0.1U_Z 0.1U_ZA1DIMM_A Reverse H:8mm12&Address: 00&+0.75VS 1 C144 0.1U_Z C145 2.2U_V6K R114 10K_0402_5% R115 10K_0402_5%205G1G2206FOX_AS0A621-J8RG-7H CONN@222Security Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet11THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2Size Document Number Custom Date: Friday, March 04, 2011 11 of 572DDR_A_D40 DDR_A_D41DDR_A_D44 DDR_A_D451DDR_A_D34 DDR_A_D3573 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT274 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204DDR_CKE1_DIMMA DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 M_ODT1DDR_CKE1_DIMMA 6 12DDR_A_D28 DDR_A_D291111111@12222222M_CLK_DDR1 6 M_CLK_DDR#1 6 DDR_A_BS1 6 DDR_A_RAS# 6 DDR_CS0_DIMMA# 6 M_ODT0 6 M_ODT1 6 +VREF_CA C138 2.2U_V6K+1.5V1R104 1K_0402_1%Layout Note: Place near JDIMM1.203,204DDR_A_D36 DDR_A_D37 112+0.75VS R105 1K_0402_1%12222SDGDDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1DDR3_DRAMRST# 6,12All VREF traces should have 10 mil trace widthDDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19Layout Note: Place near JDIMM1C126 1U_V6KC127 1U_V6KC128 1U_V6KC129 1U_V6KDDR_A_D22 DDR_A_D23C137 330U_D2_2V_YC130 10U_V6MC131 10U_V6MC132 10U_V6MC133 10U_V6MC134 10U_V6MC135 10U_V6MC136 10U_V6MC+C139 0.1U_ZDDR_A_D38 DDR_A_D39BC140 1U_V6KC141 1U_V6KC142 1U_V6KC143 1U_V6K54321+1.5VM3 support7 SB_DIMM_VREFDQR116 0_0402_5% @ 1 21 R117 1K_+1.5V JDIMM2 +DIMM1_VREF C146 2.2U_V6K C147 0.1U_Z DDR_B_D0 DDR_B_D1 1 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 205 207 VREF_DQ VSS DQ0 DQ1 VSS DM0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12/BC# A9 VDD A8 A5 VDD A3 A1 VDD CK0 CK0# VDD A10/AP BA0 VDD WE# CAS# VDD A13 S1# VDD TEST VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SA0 VDDSPD SA1 VTT GND1 BOSS1 VSS DQ4 DQ5 VSS DQS0# DQS0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 RESET# VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS CKE1 VDD A15 A14 VDD A11 A7 VDD A6 A4 VDD A2 A0 VDD CK1 CK1# VDD BA1 RAS# VDD S0# ODT0 VDD ODT1 NC VDD VREF_CA VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS EVENT# SDA SCL VTT GND2 BOSS2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72+1.5V226,11,14 DRAMRST_CNTRL_PCH 2D23 Q9 BSS138_NL_SOT23-3 @11DDR_B_D4 DDR_B_D5 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D6 DDR_B_D7 DDR_B_D12 DDR_B_D13 DDR3_DRAMRST# DDR_B_D14 DDR_B_D15 DDR_B_D20 DDR_B_D21 C148 1U_V6K C149 1U_V6K C150 1U_V6K111222DDR_B_D24 DDR_B_D25DDR_B_D28 DDR_B_D29 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_D30 DDR_B_D31DDR_B_D26 DDR_B_D27+1.5V DDR_CKE3_DIMMB DDR_B_MA15 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_BS1 DDR_B_RAS# DDR_CS2_DIMMB# M_ODT2 M_ODT3 +VREF_CB C160 1U_V6K M_CLK_DDR3 6 M_CLK_DDR#3 6 DDR_B_BS1 6 DDR_B_RAS# 6 DDR_CS2_DIMMB# 6 M_ODT2 6 M_ODT3 6 2 1 R119 1K_0402_1% &BOM Structure& DDR_CKE3_DIMMB 6 C152 10U_V6MLayout Note: Place near JDIMMB6 DDR_CKE2_DIMMBCDDR_CKE2_DIMMB DDR_B_BS2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA16 DDR_B_BS26 M_CLK_DDR2 6 M_CLK_DDR#2 6 DDR_B_BS0 6 DDR_B_WE# 6 DDR_B_CAS# 6 DDR_CS3_DIMMB#M_CLK_DDR2 M_CLK_DDR#2 DDR_B_MA10 DDR_B_BS0 DDR_B_WE# DDR_B_CAS# DDR_B_MA13 DDR_CS3_DIMMB#DDR_B_D32 DDR_B_D33 DDR_B_DQS#4 DDR_B_DQS4BDDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 +3VS +3VS DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 C166 0.1U_Z C167 2.2U_V6K 1 1R129 10K_DDR_B_D58 DDR_B_D59+0.75VSA74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 2082DDR_B_D18 DDR_B_D19DDR_B_D22 DDR_B_D231111111222222+1.5VLayout Note: Place near JDIMMB.203,204+0.75VS111DDR_B_D36 DDR_B_D37 11R120 1K_0402_1% &BOM Structure& 2222DDR_B_D38 DDR_B_D39 DDR_B_D44 DDR_B_D45 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_D46 DDR_B_D47 DDR_B_D52 DDR_B_D5322121211221&Address: 01&2S GDDDR_B_DQS#[0..7] DDR_B_DQS[0..7] DDR_B_D[0..63] 66 6R118 1K_0402_1%DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9DDR_B_MA[0..15]6DAll VREF traces should have 10 mil trace widthDDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2DDR3_DRAMRST# 6,11+1.5VC151 1U_V6KC153 10U_V6MC154 10U_V6MC155 10U_V6MC156 10U_V6MC157 10U_V6MC158 10U_V6M @CC161 1U_V6KC162 1U_V6KC163 1U_V6KC164 2.2U_V6KC165 0.1U_ZBDDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 D_CK_SDATA D_CK_SCLK +0.75VSAD_CK_SDATA 11,14 D_CK_SCLK 11,14R130 10K_0402_5%FOX_AS0A621-U4RG-7H CONN@Security Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet1DIMM_B Reverse type H:4mm5 4THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.3 2Size Document Number Custom Date: Friday, March 04, 2011 12 of 5754321PCH_RTCX1 1 R131 2 10M_.768KHZ_12.5PF_Q13MC PCH_RTCX21 OSC Y1 18P_J 1OSC41 2C168 2C169 18P_JDNC 2D3NC+3VS SERIRQ SM_INTRUDER# PCH_INTVRMEN JCMOS1 0_0603_5% @ PCH_RTCX1 PCH_RTCX2 2 PCH_RTCRST# PCH_SRTCRST# 1 JME1 0_ SM_INTRUDER# PCH_INTVRMEN 1 1 U3A A20 C20 D20 G22 K22 C17 RTCX1 RTCX2 RTCRST# SRTCRST# INTRUDER# INTVRMEN FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3 FWH4 / LFRAME# C38 A38 B37 C37 D36 E36 K36 V5 AM3 AM1 AP7 AP5 AM10 AM8 AP11 AP10 AD7 AD5 AH5 AH4 AB8 AB10 AF3 AF1 Y7 Y5 AD3 AD1 Y3 Y1 AB3 AB1 Y11 Y10 AB12 AB13 AH1 SATA3_COMP RBIAS_SATA3 R162 SATA_COMP R156 37.4_ 2 R157 49.9_ 2 1 +1.05VS_PCH SATA_PRX_DTX_N2 SATA_PRX_DTX_P2 SATA_PTX_DRX_N2 SATA_PTX_DRX_P2 34 34 34 34 SERIRQ SERIRQ 39 34 34 34 34 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 39 39 39 39 PCH_SATALED# PCH_GPIO21 R134 R136 R139 2 2 2 1 10K_ 10K_ 10K_0402_5%+RTCVCC R132 1 R133 1 2 1M_ 330K_0402_5% +RTCVCC C170 1U_K2INTVRMEN*+3VSH Integrated VRM enable L Integrated VRM disable(INTVRMEN should always be pull high.)C171 1U_K R135 1 @ 2 1K_0402_5% HDA_SPKR@ 2 2RTC1 2 R137 20K_ 2 R138 20K_0402_5%LPCLPC_FRAME# 39LDRQ0# LDRQ1# / GPIO23 SERIRQ SATA0RXN SATA0RXP SATA0TXN SATA0TXP SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA2RXN SATA2RXP SATA2TXN SATA2TXPSATA 6GHDA_BIT_CLK HDA_SYNC 42 HDA_SDOUT 42 HDA_SDIN0 HDA_SDIN0 HDA_SPKR HDA_SPKR HDA_RST#N34 L34 T10 K34 E34 G34 C34 A34*HIGH= Enable ( No Reboot ) LOW= Disable (Default)+3VALW_PCH 2 R140 1K_0402_5% @ 1 R141 0_ 1HDA_BCLK HDA_SYNC SPKR HDA_RST# HDA_SDIN0 HDA_SDIN1SATA_PRX_DTX_N0 SATA_PRX_DTX_P0 SATA_PTX_DRX_N0 SATA_PTX_DRX_P0SPI ROM FOR ME ( 4MByte )HDDPCH_SPI_WP# R142 1 2 2 +3VS 3.3K_.3K_0402_5%CPCH_SPI_HOLD# R144 1CPlease short PJP35 ODD+3VS C172 1 2 8 3 PCH_SPI_SO_R U4 VCC W HOLD S C D Q VSS39HDA_SDOHDA_SDOR145 0_ 2PCH_SPI_SO*ME debug mode,this signal has a weak internal PD Low = Disabled (Default) High = Enabled [Flash Descriptor Security Overide]+3VALW_PCH R143 2 1 1K_0402_5% HDA_SYNC HDA_SDOUTIHDAHDA_SDIN2 HDA_SDIN3 HDA_SDOSATAA36 C36 N32SATA3RXN SATA3RXP SATA3TXN SATA3TXP SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP0.1U_Z PCH_SPI_WP#4PCH_SPI_HOLD# 7 PCH_SPI_CS# 1 R149 PCH_SPI_CLK 1 R150 PCH_SPI_SI 1 R154 PCH_SPI_CS#_R 2 0_0402_5% PCH_SPI_CLK_R 2 0_0402_5% PCH_SPI_SI_R 2 0_ 6 5HDA_DOCK_EN# / GPIO33 HDA_DOCK_RST# / GPIO13This signal has a weak internal pull-down On Die PLL VR Select is supplied by 1.5V when sampled high 1.8V when sampled low Needs to be pulled High for Huron River platfromR147 33_ 2 HDA_BIT_CLK R148 33_0402_5% HDA_SYNC_R 1 2 R151 33_ 2 HDA_RST# R155 33_ 2 HDA_SDOUT_R R153 51_ 1*PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO2PCH_SPI_SO_RJ3 H7 K5 H1JTAG_TCKW25Q32BVSSIGJTAGJTAG_TMS JTAG_TDI JTAG_TDOSATAICOMPO SATAICOMPI SATA3RCOMPO SATA3COMPIP/N:SA+1.05VS_PCH C173 R158 22P_J @ 33_0402_5% @ 2 1 1 2PCH_SPI_CLK_R42 HDA_BITCLK_AUDIO 42 HDA_SYNC_AUDIOBReserve for EMIPCH_SPI_CLK PCH_SPI_CS# T3 Y14 T1 PCH_SPI_SI V4 U3 SPI_CLK SPI_CS0# SATA3RBIAS 2 750_0402_1%B42 HDA_RST_AUDIO# 42 HDA_SDOUT_AUDIOSPISPI_CS1# SPI_MOSI SPI_MISOSATALED# SATA0GP / GPIO21 SATA1GP / GPIO19P3 V14 P1PCH_SATALED# PCH_GPIO21 PCH_GPIO19PCH_SATALED# 41+3VALW_PCH 1+3VALW_PCH 1+3VALW_PCH 1PCH_SPI_SO+3VS 1 R674 4.7K_0402_5% @ PCH_GPIO19 2COUGARPOINT_FCBGA989~D R161 200_0402_5% @R159 200_0402_5% @ 2 2 PCH_JTAG_TDO R163 100_0402_1% @ 2 2R160 200_0402_5% @ PCH_JTAG_TMS 2 1PCH_JTAG_TDI R165 100_0402_1% @11Prevent back drive issue.+3VS Q10 BSS138_NL_SOT23-3 1HDA_SYNC D 2 GPrevent back drive issue.+3VS Q65 BSS138_NL_SOT23-3 1HDA_SDOUT D 2 GR164 100_0402_1% @ 2Debug Port DG 1.2 PH 4.7K +3VSHDA_SYNC_R3 S @HDA_SDOUT_R3 S @W=20mils+RTCBATTAtrace width 10mil+CHGRTC D1 2 1 3W=20mils+RTCVCC1212AR152 0_R768 0_0402_5%R166 1K_ 1R747 1M_C174 0.1U_Z2BAS40-04_SOT23-3Security Classification 9/29 DG1.5 Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet12THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2Size Document Number Custom Date: Friday, March 04, 2011 13 of 5754321U3B 35 PCIE_PRX_DTX_N1 35 PCIE_PRX_DTX_P1 35 PCIE_PTX_C_DRX_N1 35 PCIE_PTX_C_DRX_P1 37 PCIE_PRX_DTX_N2 37 PCIE_PRX_DTX_P2 37 PCIE_PTX_C_DRX_N2 37 PCIE_PTX_C_DRX_P2 38 PCIE_PRX_DTX_N3 38 PCIE_PRX_DTX_P3 38 PCIE_PTX_C_DRX_N3 38 PCIE_PTX_C_DRX_P3 44 PCIE_PRX_DTX_N4 44 PCIE_PRX_DTX_P4 44 PCIE_PTX_C_DRX_N4 44 PCIE_PTX_C_DRX_P4 PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P1 PCIE_PTX_DRX_N1 PCIE_PTX_DRX_P1 PCIE_PRX_DTX_N2 PCIE_PRX_DTX_P2 PCIE_PTX_DRX_N2 PCIE_PTX_DRX_P2 PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PCIE_PTX_DRX_N3 PCIE_PTX_DRX_P3 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 BG34 BJ34 AV32 AU32 BE34 BF34 BB32 AY32 BG36 BJ36 AV34 AU34 BF36 BE36 AY34 BB34 BG37 BH37 AY36 BB36 R175 R176 R181 +3VALW_PCH R178 R180 2 2 1 10K_ 10K_0402_5% PCH_GPIO73 PCH_GPIO25 2 2 2 1 10K_ 10K_ 10K_0402_5% PCH_GPIO18 PCH_GPIO20 PCH_GPIO26 BJ38 BG38 AU36 AV36 BG40 BJ40 AY40 BB40 BE38 BC38 AW38 AY38 Y40 Y39 PCH_GPIO73 CLK_PCIE_MINI1# CLK_PCIE_MINI1 R187 2 1 0_0402_5% PCH_GPIO18 J2 AB49 AB47 M1 AA48 AA47 1 0_0402_5% PCH_GPIO20 V10 Y37 Y36 2 0_0402_5% PCH_GPIO25 A8 Y43 Y45 2 0_0402_5% PCH_GPIO26 L12 V45 V46 PCH_GPIO44B+3VALW_PCH LID_SW_OUT# SMBALERT# / GPIO11 SMBCLK SMBDATA E12 H14 C9 LID_SW_OUT# PCH_SMBCLK PCH_SMBDATA LID_SW_OUT# 39 PCH_SMBCLK 37 PCH_SMBDATA 37 PCH_SMBCLK PCH_SMBDATA R168 R169 R170 R171 R172 R174 1 1 1 1 1 1 2 2 2 2 2 2 2.2K_.2K_K_0402_5%DPCIE LANC175 C1761 12 0.1U_K 2 0.1U_KPERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5 PERN6 PERP6 PETN6 PETP6 PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8 CLKOUT_PCIE0N CLKOUT_PCIE0PR173 R1671 12 210K_K_0402_5%DRAMRST_CNTRL_PCHMini CardSMBUSC177 C1781 12 0.1U_K 2 0.1U_KSML0ALERT# / GPIO60 SML0CLK SML0DATAA12 DRAMRST_CNTRL_PCH C8 G12DRAMRST_CNTRL_PCH 6,11,12PCH_GPIO74 PCH_SML1CLK PCH_SML1DATADCard ReaderC179 C1801 12 0.1U_K 2 0.1U_K2.2K_.2K_K_0402_5%USB3.0C181 C1821 12 0.1U_K 2 0.1U_KSML1ALERT# / PCHHOT# / GPIO74C13 E14 M16PCH_GPIO74 PCH_GPIO47 PCH_SML1CLK PCH_SML1DATAPCI-E*SML1CLK / GPIO58 SML1DATA / GPIO75For DDR+3VS R177 4.7K_ 2 +3VS 1 D_CK_SDATA R179 4.7K_ 2 +3VS 4 D_CK_SCLK D_CK_SCLK 11,12 D_CK_SDATA 11,12+3VSControllerCL_CLK1LinkCL_DATA1 CL_RST1#T11 P10PCH_SMBDATA 6 Q11A DMN66D0LDW-7_SOT363-62 PCH_SMBCLK PCH_GPIO47 3 Q11B DMN66D0LDW-7_SOT363-6 5M7R182 R183C2 2 21 10K_ 10K_ 10K_0402_5%PCH_GPIO44 PCH_GPIO45 PCH_GPIO46PEG_A_CLKRQ# / GPIO47 CLKOUT_PEG_A_N CLKOUT_PEG_A_P CLKOUT_DMI_N CLKOUT_DMI_P CLKOUT_DP_N / CLKOUT_BCLK1_N CLKOUT_DP_P / CLKOUT_BCLK1_P CLKOUT_PCIE2N CLKOUT_PCIE2P PCIECLKRQ2# / GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3# / GPIO25 CLKIN_DOT_96N CLKIN_DOT_96P CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4# / GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P PCIECLKRQ5# / GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P PEG_B_CLKRQ# / GPIO56 XCLK_RCOMP CLKOUT_PCIE6N CLKOUT_PCIE6P PCIECLKRQ6# / GPIO45 CLKIN_SATA_N / CKSSCD_N CLKIN_SATA_P / CKSSCD_P REFCLK14IN CLKIN_PCILOOPBACK XTAL25_IN XTAL25_OUT CLKIN_DMI_N CLKIN_DMI_P CLKIN_DMI2_N CLKIN_DMI2_PM10 AB37 AB38CLOCKSR184PCIECLKRQ0# / GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1# / GPIO18C+3VS AV22 AU22 AM12 AM13 BF18 BE18 BJ30 BG30 G24 E24 AK7 AK5 K45 H45 V47 V49 CLK_CPU_DMI# CLK_CPU_DMI CLK_CPU_DPLL# CLK_CPU_DPLL CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI CLKIN_DMI2# CLKIN_DMI2 CLK_BUF_DREF_96M# CLK_BUF_DREF_96M CLK_BUF_PCIE_SATA# CLK_BUF_PCIE_SATA CLK_BUF_ICH_14M CLK_BUF_DREF_96M# CLK_BUF_DREF_96M CLK_PCI_LPBACK XTAL25_IN XTAL25_OUT R208 90.9_ 2 +1.05VS_PCH CLK_PCI_LPBACK 17 CLK_BUF_PCIE_SATA# CLK_BUF_PCIE_SATA CLK_BUF_ICH_14M R201 R202 R203 R204 R207 CLK_BUF_CPU_DMI# CLK_BUF_CPU_DMI CLKIN_DMI2# CLKIN_DMI2 R196 R197 R199 R200 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 10K_K_K_K_K_K_K_K_K_0402_5%B37 MINI1_CLKREQ#USB3.044 CLK_PCIE_USB30# 44 CLK_PCIE_USB30 44 USB30_CLKREQ#CLK_PCIE_USB30# CLK_PCIE_USB30 R190 2CLK_CPU_DPLL# 5 CLK_CPU_DPLL 5120MHz for eDP.PCH_SML1DATA 6 Q12A DMN66D0LDW-7_SOT363-6 PCH_SML1CLK2Mini Card37 CLK_PCIE_MINI1# 37 CLK_PCIE_MINI1CLK_CPU_DMI# 5 CLK_CPU_DMI 5Pull up at EC side.1 EC_SMB_DA2 EC_SMB_DA2 22,395PCIE LAN35 CLK_PCIE_LAN# 35 CLK_PCIE_LAN 35 LAN_CLKREQ#CLK_PCIE_LAN# CLK_PCIE_LAN R193 134EC_SMB_CK2EC_SMB_CK2 22,39Q12B DMN66D0LDW-7_SOT363-6Card Reader38 CLK_PCIE_CARD# 38 CLK_PCIE_CARD 38 CARD_CLKREQ#CLK_PCIE_CARD# CLK_PCIE_CARD R198 1L14 AB42 AB4022 CLK_PEG_VGA# 22 CLK_PEG_VGACLK_PEG_VGA# CLK_PEG_VGA PEG_CLKREQ#_RE6 V40 V42Y47XCLK_RCOMPXTAL25_IN XTAL25_OUT CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67 K43 CLK_FLEX0 F47 1 H47 K49 DGPU_PRSNT# +3VS 1 C183 27P_J @ T12 2 1 R209 Y2 1 1 2 R219 33_0402_5% @ 2 1 C184 27P_J 2 1M_0402_5%PCH_GPIO45T13 V38 V37PCH_GPIO46K12 AK14 AK13PCIECLKRQ7# / GPIO46 CLKOUT_BCLK0_N / CLKOUT_PCIE8N CLKOUT_BCLK0_P / CLKOUT_PCIE8P COUGARPOINT_FCBGA989~DFLEX CLOCKSCLKOUT_PCIE7N CLKOUT_PCIE7P25MHZ_20PF_7A+3VALW_PCH 1 DGPU_PRSNT# R216 10K_AR214 10K_0402_5% UMAO@ 2GPIO67VGA_ON 17,25,46,55 DGPU_PRSNT# Q13 2N7002E_SOT23-3 R220 OPT@ 0_ 1 OPT@ 2 S 1 R222 2.2K_0402_5% @ 22R218 10K_0402_5% OPT@ 12CLK_PCI_LPBACKC186 22P_J @ 1 2APEG_CLKREQ#_R 1Pull high @ VGA sidePEG_CLKREQ# 221 DOPTIMUS UMASecurity Classification Issued Date0 12 GReserve for EMI please close to UH4for safe2R221 2.2K_0402_5% @Compal Secret Data Deciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet1THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2Size Document Number Custom Date: Friday, March 04, 2011 14 of 5754321DDU3C 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 SYS_PWROK DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 BC24 BE20 BG18 BG20 BE24 BC20 BJ18 BJ20 AW24 AW20 BB18 AV18 AY24 AY20 AY18 AU18 BJ24 DMI_IRCOMP 2 49.9_0402_1% RBIAS_CPY 2 750_0402_1% BG25 BH21 DMI0RXN DMI1RXN DMI2RXN DMI3RXN DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP DMI_ZCOMP DMI_IRCOMP DMI2RBIAS FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI_INT OUT +1.05VS_PCH 1 R226 1 R227 FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1 BJ14 AY14 BE14 BH13 BC12 BJ12 BG10 BG9 BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9 AW16 AV12 BC10 AV14 BB10 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4DMI+3VS 5FDIR22312 0_0402_5%+RTCVCCVCC39 PCH_PWROK 54 VGATE1 2FDI_INT 4 FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1 4 4 4 4IN1 IN2DSWODVRENR224 R2252 2 @1 330K_ 330K_0402_5%GNDCU5 MC74VHC1G08DFT2G_SC70-5 @ SYS_PWROK*R22821 10K_0402_5%4mil width and place within 500mil of the PCHDSWODVREN - On Die DSW VR Enable H Enable L Disable3CDSWVRMENA18 E22 B9 N3 G8 N14 D10 H4 F4 G10 G16 AP14 K14DSWODVREN PCH_RSMRST#_R R230 0_0402_5% WAKE# 1 2 PCH_GPIO32 WAKE# SUS_STAT# SUSCLK @ T16 PM_SLP_S5# 39 @ T17 PM_SLP_S4# 39 @ PM_SLP_S3# SLP_A# PM_SLP_SUS# H_PM_SYNC PCH_GPIO29 @ @ @ T64 T19 T20 H_PM_SYNC 5 T18 PM_SLP_S3# 39 PCH_GPIO32 R236 1 @ 2 10K_0402_5% PM_SLP_S5# PM_SLP_S4# @ T15 PCH_GPIO29 R232 R234 1 1 2 10K_ 10K_0402_5% +3VS 2 8.2K_0402_5%System Power ManagementHave internal PUR231 0_0402_5% @ 2 1 5 XDP_DBRESET# SUSWARN#_R PCH_PWROK R233 R229 1SUSACK#_RC12 K3 P12 L22 L10SUSACK# SYS_RESET# SYS_PWROK PWROK APWROK DRAMPWROK RSMRST#DPWROK WAKE# CLKRUN# / GPIO32 SUS_STAT# / GPIO61 SUSCLK / GPIO62 SLP_S5# / GPIO63 SLP_S4#not support Deep S4,S5 DPWROK mux with PWROK check list1.0 P.42PCH_PCIE_WAKE# 35,37,44 +3VALW_PCH2 XDP_DBRESET#_R 0_0402_5% SYS_PWROK PCH_PWROK_R 0_0402_5%SUSACK#_R12SUSCLK 39R750 15 PM_DRAM_PWRGD 39 PCH_RSMRST# 1PM_DRAM_PWRGD PCH_RSMRST#_R 2 0_0402_5% SUSWARN#_RB13 C21 K16 E20 H20 E10 A10R237EC team suggestion South Bridge side must have pull-low 10K on this pin(GPIO32)SUSWARN# / SUS_PWR_DN_ACK / GPIO30 SLP_S3# PWRBTN# ACPRESENT / GPIO31 BATLOW# / GPIO72 RI# COUGARPOINT_FCBGA989~D SLP_A# SLP_SUS# PMSYNCH SLP_LAN# / GPIO29+3VSBR23921 200_0402_5%PM_DRAM_PWRGD39 PBTN_OUT# 39,46,48 ACIN1 R238 D2 1PBTN_OUT#_R 2 0_ PCH_ACINCan be left NC when IAMT is not support on the platfrom not support Deep S4,S5 can NC PCH EDS1.2 P.74B+3VALW_PCH R240 R241 R242 R243 2 2 2 2 1 10K_ 200K_ 10K_ 10K_0402_5% SUSWARN#_R PCH_ACIN PCH_GPIO72 RI#RB751V-40_SOD323-2 PCH_GPIO72 RI#R24421 10K_0402_5%PCH_RSMRST#_RAASecurity Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet1THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2Size Document Number Custom Date: Friday, March 04, 2011 15 of 5754321DD1R246 100K_ U3D ENBKL J47 M45 P45 PCH_LCD_CLK PCH_LCD_DATA CTRL_CLK CTRL_DATA T40 K47 T45 P39 AF37 AF36 AE48 AE47 AK39 AK40 AN48 AM47 AK47 AJ48 AN47 AM49 AK49 AJ47 AF40 AF39 AP43 AP45 AM42 AM40 AP39 AP4039 31 31ENBKL PCH_ENVDD DPST_PWML_BKLTEN L_VDD_EN L_BKLTCTL L_DDC_CLK L_DDC_DATA L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3SDVO_TVCLKINN SDVO_TVCLKINP SDVO_STALLN SDVO_STALLP SDVO_INTN SDVO_INTP31 PCH_LCD_CLK 31 PCH_LCD_DATASDVO_CTRLDATA strap pull high at level shift pageSDVO_SCLK SDVO_SDATA SDVO_SCLK 33 SDVO_SDATA 33R247 +3VS R248 R250 1 1 2 2.2K_ 2.2K_0402_5% CTRL_CLK CTRL_DATA R2492.37K_ 1 0_ 1LVDS_IBG LVD_VREFSDVO_CTRLCLK SDVO_CTRLDATA DDPB_AUXN DDPB_AUXP DDPB_HPDP38 M39LVDS31 31 +3VSCPCH_TXCLKPCH_TXCLK+ PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+PCH_TXCLKPCH_TXCLK+ PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2PCH_TXOUT0+ PCH_TXOUT1+ PCH_TXOUT2+AT49 AT47 AT40 PCH_DPB_HPD AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49 P46 P42 AP47 AP49 AT38 AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49 M43 M36 AT45 AT43 BH41 BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42 PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3PCH_DPB_HPD 33 PCH_DPB_N0 PCH_DPB_P0 PCH_DPB_N1 PCH_DPB_P1 PCH_DPB_N2 PCH_DPB_P2 PCH_DPB_N3 PCH_DPB_P3 33 33 33 33 33 33 33 33Digital Display InterfaceR470 1 R471 12 2.2K_ 2.2K_0402_5%PCH_LCD_CLK PCH_LCD_DATA31 31 31 31 31 31DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3PHDMI D2 HDMI D1 HDMI D0 HDMI CLKC+3VS R251 R252 1 1 2 2.2K_ 2.2K_0402_5% PCH_CRT_CLK PCH_CRT_DATAAH45 AH47 AF49 AF45 AH43 AH49 AF47 AF43R253 R254 R2551 1 12 150_ 150_ 150_0402_1%PCH_CRT_B PCH_CRT_G PCH_CRT_R 32 PCH_CRT_B 32 PCH_CRT_G 32 PCH_CRT_R 32 PCH_CRT_CLK 32 PCH_CRT_DATA PCH_CRT_B PCH_CRT_G PCH_CRT_R PCH_CRT_CLK PCH_CRT_DATA PCH_CRT_HSYNC PCH_CRT_VSYNC CRT_IREF 1N48 P49 T49 T39 M40 M47 M49 T43 T42CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN COUGARPOINT_FCBGA989~DBCRTB32 PCH_CRT_HSYNC 32 PCH_CRT_VSYNCR256 1K_% 2AASecurity Classification Issued Date Compal Secret DataDeciphered Date TitleCompal Electronics, Inc.SCHEMATIC, MB LA-7231P4019BLRev B Sheet1THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.5 4 3 2Size Document Number Custom Date: Friday, March 04, 2011 16 of 5754321+3VS RP1 8 7 6 5 1 2 3 4 PCI_PIRQA# PCI_PIRQD# PCI_PIRQC# PCI_PIRQB# BG26 BJ26 BH25 BJ16 BG16 AH38 AH37 AK43 AK45 C18 N30 H3 AH12 AM4 AM5 Y13 K24 L24 AB46 AB45U3E NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 NV_DQS0 NV_DQS1 NV_DQ0 / NV_IO0 NV_DQ1 / NV_IO1 NV_DQ2 / NV_IO2 NV_DQ3 / NV_IO3 NV_DQ4 / NV_IO4 NV_DQ5 / NV_IO5 NV_DQ6 / NV_IO6 NV_DQ7 / NV_IO7 NV_DQ8 / NV_IO8 NV_DQ9 / NV_IO9 NV_DQ10 / NV_IO10 NV_DQ11 / NV_IO11 NV_DQ12 / NV_IO12 NV_DQ13 / NV_IO13 NV_DQ14 / NV_IO14 NV_DQ15 / NV_IO15 NV_ALE NV_CLE NV_RCOMP NV_RB# BE28 BC30 BE32 BJ32 BC28 BE30 BF32 BG32 AV26 BB26 AU28 AY30 AU26 AY26 AV28 AW30 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 TP39 TP40 NV_RE#_WRB0 NV_RE#_WRB1 NV_WE#_CK0 NV_WE#_CK1 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P USBRBIAS# USBRBIAS PME# PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4 COUGARPOINT_FCBGA989~D R265 0_0402_5% @ 2 1 +3VS 5 5 OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43 OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14 A14 K20 B17 C16 L16 A16 D14 C14 USB_OC0# USB_OC1# USB_OC2# USB_OC3# USB_OC4# USB_OC5# USB_OC6# USB_OC7# USB_OC0# 37 AY7 AV7 AU3 BG4 AT10 BC8 AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6 AV5 AY1 AV10 AT8 DF_TVS8.2K_R_5%DRP2 8 7 6 5 1 2 3 4 PCH_GPIO55 PCH_GPIO51 PCH_GPIO5 PCH_GPIO528.2K_R_5% RP3 8 7 6 5 1 2 3 4 PCH_GPIO53 PCH_GPIO2 PCH_GPIO4 ODD_DA#8.2K_R_5% R185 10K_ OPT@ 2 B21 M20 AY16 BG46 TP21 TP22 TP23 TP24VGA_ONRSVDTP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 TP20DNVRAMDMI Termination Voltage Set to Vcc when HIGH DF_TVS Set to Vss when LOWR25812 8.2K_ 100K_0402_5%DGPU_HOLD_RST# PLT_RST#AY5 BA2 AT12 BF3 C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32 C33 B33 USB20_N0 USB20_P0 USB20_N1 USB20_P1R259 1DG1.2 CRB1.0 PH 2.2K series 1K+1.8VS USB20_N0 USB20_P0 USB20_N1 USB20_P1 37 37 37 37USB/B (Right side) USB/B (Right side)DF_TVS R261 2C1R260 2.2K_C1 1K_0402_5%H_SNB_IVB# 5CLOSE TO THE BRANCHING POINTPCIPCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD# DGPU_HOLD_RST# PCH_GPIO52 VGA_ON PCH_GPIO51 PCH_GPIO53 PCH_GPIO55 PCH_GPIO2 ODD_DA# PCH_GPIO4 PCH_GPIO5 @ PLT_RST# CLK_PCI0 CLK_PCI1 CLK_PCI2 CLK_PCI3 CLK_PCI4K40 K38 H38 G38 C46 C44 E40 D47 E42 F46 G42 G40 C42 D44 K10 C6 H49 H43 J48 K42 H40PIRQA# PIRQB# PIRQC# PIRQD# REQ1# / GPIO50 REQ2# / GPIO52 REQ3# / GPIO54 GNT1# / GPIO51 GNT2# / GPIO53 GNT3# / GPIO55 PIRQE# / GPIO2 PIRQF# / GPIO3 PIRQG# / GPIO4 PIRQH# / GPIO5Some PCH config not support USB port 6 & 7.USB2}