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（毕业论文）基于ads的低噪声放大器设计
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折叠共源共栅低噪声放大器设计(可编辑),低噪声放大器,共源共栅,共源共栅结构,栅源电压,mos栅源极并联电阻,低噪声风机箱,低噪声,低噪声管,低噪声功放
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3秒自动关闭窗口上传用户：lcmzguuqfz资料价格：5财富值&&『』文档下载 ：『』&&『』学位专业：&关 键 词 ：&&&&&&&权力声明：若本站收录的文献无意侵犯了您的著作版权，请点击。摘要:（摘要内容经过系统自动伪原创处理以避免复制，下载原文正常，内容请直接查看目录。）跟着无线通讯技巧的成长，高集成、小型化和低功耗成了无线通讯的主要特点。高集成和小型化的一个主要成长偏向是将一切的集成电路高度集成到单个封装体系中从而削减核心电路和元器件完成小型化；而高度集成的封装体系，个中电能将转化成热能从而成为影响体系机能潜伏风险，能耗成绩成了全部体系集成的症结成绩。CMOS工艺的射频芯片因为工艺便宜和高集成度的特色在封装体系中占领有主要位置。关于封装体系中器件而言，其功耗和其供电电压成平方关系，故下降器件的任务电压是下降器件功耗的有用手腕之一。同时，关于一些可植入式医疗器件、无线传感器收集、无线遥测收集等平日采取小的电池或情况的能量来供电，在这类情形下须要包管全部器件或无线体系可以或许在低电压下任务。但是，关于这些体系中焦点部门射频前端而言，低任务电压将招致体系的机能变差乃至没法正常任务，是以若何在低任务电压的情形下包管电路的机能成为集成电路设计挑衅任务。另外一方面，小我无线通讯技巧的成长令人们对无线传输的速度和带宽提出了更高的请求，而传统的低频段(3 GHz以下)因为日趋拥堵没法知足速度成长的请求，传输速度和带宽曾经成为制约无线技巧成长的症结成绩。这类日趋拥堵的低频段频率资本和人们对传输速度和带宽请求的抵触增进了无线通讯载波频率正在向更高频率成长。本文的研讨任务重要针对封装体系中CMOS工艺射频电路的低电压和高频电路设计这两个方面来停止的。起首，第二章研讨了cascode低噪声缩小器的低电压低功耗技巧。Cascode构造因为具有优越的反向隔离在低噪声缩小器中获得了普遍的运用，然则因为cascode构造MOS管的分列特色，该构造难以完成低电压下任务；同时，其任务电流和射频机能亲密相干，任务电流的下降将招致其机能变差。为战胜cascode构造的这些缺陷，文中经由过程采取直流电流分别和正向体偏置技巧来完成任务电压下降和任务电流削减，进而完成总功耗下降。文中具体研讨了这类低电压电路构造的电路设计并经由过程试验验证了其有用性，试验成果注解，本章设计的低电压cascode缩小器可以在0。5 V电压下任务，总功耗只要传统cascode低噪声缩小器的30%阁下，而两者射频机能相当。关于低噪声缩小器而言，别的一种普遍运用的构造是多级级联络构。因为多级级联低噪声缩小器平日由多个单级缩小器组成，在本文的第三章起首剖析了单级低噪声缩小器的噪声、增益与任务频率的关系，为后续的多级电路设计供给实际指点。关于单级缩小器而言，其场效应管的栅漏电容组成了旌旗灯号的反应通道，该反应将对电路的婚配和增益发生影响。文中实际剖析了栅漏电容对单级缩小器的特征影响，并将剖析的结论运用到多级低噪声缩小器的剖析和设计中。应用剖析的结论和正向体偏置技巧，文中设计了0。5 V X波段低噪声缩小器来验证剖析的成果，测试成果注解，该低电压低噪声缩小器在射频机能相当的前提下，功耗获得了年夜幅度下降。为进一步下降多级缩小器的功耗，文中研讨了电流复用和正向体偏置混杂应用技巧，经由过程对电路剖析，公道设置其任务偏置电压可以或许完成功耗进一步下降，并经由过程详细的运用电路验证了剖析、设计成果。因为CMOS工艺的衬底绝对与其他工艺的低电阻率和低特点频率，当任务频率上升到K波段时，传统几吉赫兹(GHz)CMOS电路设计办法面对着窘境， CMOS工艺高频电路的设计是一个难点。文中第四章剖析和研讨了CMOS工艺K波段(21 GHz)低电压低噪声缩小器的优化偏置和进步增益的技巧。经由过程优化偏置电压，防止了传统高线性度偏置电压的增益低和任务电压规模窄的缺陷；经由过程第一级电路采取弱负反应技巧完成在不增长功耗的条件下进步增益。试验成果验证了这些设计办法的有用性。K波段高集成度的CMOS单芯片收发体系在片上无线互连、汽车雷达等范畴具有普遍运用远景，而高集成度的单芯片收发体系请求个中的各个子体系具有低功耗的特征。文章的最初一部门研讨了低功耗24 GHz吸收机射频前端体系，起首剖析了全部体系架构和机能，具体的剖析了下降模块电路任务电流战略和模块电路构建，并终究仿真全部射频前端体系，仿真成果注解全部体系绝对于曾经揭橥的同类任务，射频机能相当而功耗更低。Abstract:Along with the wireless communication technology develops, Gao Jicheng, miniaturization and low power consumption has become the main features of wireless communications. High integration and miniaturization of a major growth bias is all integrated circuit is highly integrated into a single package system to reduce the core circuit and compo and highly integrated packaging system, medium power can will be transformed into heat energy, thus become influence system machine latent risk and energy consumption performance into the all system integrated the crux of the results. The RF chip CMOS process because the process is cheap and high integration features in the packaging system occupying the main position. On the packaging system, the power supply voltage and the square, so drop the task voltage of the device is one of the useful power wrist drop device. At the same time, for some implantable medical devices, wireless sensor collection, wireless telemetry collection etc. taken on a weekday, small battery or the energy to power supply, under this kind of situation need to ensure that all devices or wireless system can probably task in low voltage. But for these systems focus sectors RF front-end, low working voltage will lead to system performance variation and cannot work normally is Ruohe under low task voltage assure circuit function become integrated circuit design challenge task. On the other hand, the growth of personal wireless communication skills make people puts forward higher request to the wireless transmission speed and bandwidth, and traditional low-frequency (below 3 GHz) because increasingly crowded didn't satisfy the growth rate of the request, transmission speed and bandwidth has become crux which restricts the development of the non line skill scores. This is the low frequency congestion of capital and people to enhance the wireless communication frequency is growing up to a higher frequency of conflict request transmission speed and bandwidth. This research is important task in view of the low voltage and high frequency circuit CMOS system in package technology for RF circuit design these two aspects to stop. First of all, the second chapter discusses the cascode low noise reduction techniques for low voltage and low power consumption. Cascode structure because of the superior reverse isolation in low noise reduction is obtained the widespread use. However because cascode structure of MOS transistor breakdown characteristics, the structure difficult to complete tasks u at the same time, the working current and RF function is closely related to the, task current decline will lead to the function variation. For these defects over the cascode structure, this paper through the process of taking direct current respectively and forward body bias skills to complete the task and task of current voltage drop and the total power consumption decreased cut. This paper discusses the specific circuit of this kind of low voltage circuit structure design and through experiments to verify its usefulness, test results of notes, the design of low voltage cascode device can be reduced in 0. The voltage of 5 V, as long as the total power consumption of traditional cascode low noise amplifier of the 30% of you, and two radio frequency function is. A low noise amplifier, another commonly used is to construct multi-level contact structure. Because cascaded low noise amplifier weekdays from multiple single stage reduction device, in the third chapter analyzes the relationship between single stage low noise amplifier noise, gain and task frequency, for subsequent multilevel circuit design to provide theoretical guidance. For single stage reduction is concerned, the FET gate drain capacitance signal reaction channels, the reaction will marriage and gain of the circuit. In this paper, the actual analysis of the gate drain capacitance effect on the characteristics of single stage amplifier, and the conclusion of the analysis is applied to multilevel analysis and design for low noise reduction in. The conclusion of the analysis and application of forward body bias technique, this paper designs 0. The 5 V X band low noise amplifier to verify the analysis results, the test results of notes, the low voltage low noise amplifier based on radio frequency function under the same power, made of a large decline. For further decline in multistage amplifier power, this paper discusses the current reuse and forward body bias hybrid application skills, through the process of circuit analysis, reasonable setting the bias voltage may complete the power consumption is further reduced, and through the detailed process of using the circuit proved that the analysis and design results. Because the CMOS substrate absolute and other process of low resistivity and low characteristic frequency, when the task frequency up to K band, tradition a few gigahertz (GHz) CMOS circuit design methods face a dilemma, CMOS process high frequency circuit design is a difficulty. The fourth chapter analysis and research the CMOS technology of K band (21 GHz) technique of low voltage low noise reduced bias and gain the optimization progress of. Optimized through the process of bias voltage, prevent the traditional high linearity bias voltage gain is low and the task voltage through the first stage circuit adopt weak negative reaction skills progress gain in power does not grow under the condition of complete. The test results verify the usefulness of these design methods. K band of a high degree of integration of CMOS single chip transceiver system on chip wireless interconnection, car radar and other category has the widespread application prospect, medium and high degree of integration of the single chip transceiver system request of each subsystem of the system has characteristics of low power consumption. The first part discusses the low-power 24 GHz absorption machine RF front-end system, the first analysis of the whole system architecture and function, the specific analysis of the descent module circuit current strategy and circuit module construction, and eventually all simulation of RF front-end system, simulation results notes all system to have uncovered a similar task, RF performance and lower power consumption.目录:摘要7-9Abstract9-11第一章 绪论15-31&&&&1.1 研究背景15-17&&&&1.2 国内外研究现状17-24&&&&&&&&1.2.1. 低电压低噪声放大器的研究现状17-22&&&&&&&&1.2.2 K 波段低噪声放大器和射频前端的研究现状22-24&&&&1.3 本文的研究目标和主要内容24-26&&&&参考文献26-31第二章 cascode 低噪声放大器的低电压低功耗研究31-61&&&&2.1 引言31&&&&2.2 传统cascode 结构的局限性31-36&&&&&&&&2.2.1 工作电压的局限32-33&&&&&&&&2.2.2 工作电流的影响因素33-35&&&&&&&&2.2.3 工作频率对增益影响35-36&&&&2.3 直流分离技术的 cascode 低噪声放大器36-43&&&&&&&&2.3.1 射频和直流特性37-39&&&&&&&&2.3.2 功耗降低39&&&&&&&&2.3.3 功耗降低对射频性能的影响39-43&&&&2.4 正向体偏置技术的直流分离cascode 低噪声放大器43-47&&&&&&&&2.4.1. 正向体偏置技术43-45&&&&&&&&2.4.2. 采用正向体偏置的直流分离 cascode 低噪声放大器45-47&&&&2.5 正向体偏置的直流分离 cascode 低噪声放大器设计47-51&&&&&&&&2.5.1. 输入端匹配电路设计47-49&&&&&&&&2.5.2. 级间匹配电路设计49-51&&&&2.6 直流分离cascode低噪声放大器的实验验证51-58&&&&&&&&2.6.1. 直流分离技术的 cascode 低噪声放大器性能52-54&&&&&&&&2.6.2. 正向体偏置的直流分离 cascode 低噪声放大器性能54-56&&&&&&&&2.6.3. 实验结果的讨论56-58&&&&2.7 本章小结58-59&&&&参考文献59-61第三章 多级结构低噪声放大器的低电压低功耗研究61-93&&&&3.1 引言61&&&&3.2 单级放大器的分析61-71&&&&&&&&3.2.1 共源结构和共栅结构放大器的特性62-64&&&&&&&&3.2.2 栅漏电容对共源放大器输入和跨导影响64-70&&&&&&&&3.2.3 栅漏电容对共栅放大器输入和跨导影响70-71&&&&3.3 两级共源放大器的低电压设计71-83&&&&&&&&3.3.1. 两级共源放大器的设计72-77&&&&&&&&3.3.2. 两级共源放大器的低电压设计77-79&&&&&&&&3.3.3. 0.5 V X 波段两级共源低噪声放大器的设计及测试结果79-83&&&&3.4 电流复用的两级低电压低噪声放大器83-90&&&&&&&&3.4.1. 电流复用低电压放大器的分析84-87&&&&&&&&3.4.2. 电流复用低电压放大器的电路设计及仿真87-90&&&&3.5 本章小结90&&&&参考文献90-93第四章 K 波段低电压低噪声放大器研究93-117&&&&4.1 引言93&&&&4.2 CMOS 工艺K 波段低噪声放大器设计面临的挑战93-99&&&&&&&&4.2.1 互连线寄生参数94-96&&&&&&&&4.2.2 NMOS 管的特征频率96&&&&&&&&4.2.3 射频性能96-99&&&&4.3 提高线性度的栅极偏置电压优化99-103&&&&&&&&4.3.1 低电压电路结构选择99-100&&&&&&&&4.3.2 优化栅极偏置电压100-103&&&&4.4 提高增益的输入端栅极电阻匹配技术103-109&&&&&&&&4.4.1 传统的源极负反馈放大器103-104&&&&&&&&4.4.2 弱源极负反馈的共源放大器电路104-107&&&&&&&&4.4.3 增益转换107-109&&&&4.5 K 波段低噪声放大器的版图设计和实验109-114&&&&&&&&4.5.1 版图设计109-111&&&&&&&&4.5.2 测试结果111-114&&&&4.6 本章小结114&&&&参考文献114-117第五章 低功耗24 GHz 射频前端系统设计117-143&&&&5.1 引言117-118&&&&5.2 射频前端的系统架构和性能118-123&&&&&&&&5.2.1. 前端系统的架构118-121&&&&&&&&5.2.2. 系统的性能121-123&&&&5.3 系统模块电路的设计123-133&&&&&&&&5.3.1. 低噪声放大器的设计123-126&&&&&&&&5.3.2. 混频器的设计126-131&&&&&&&&5.3.3. 中频放大器的设计131-133&&&&5.4 系统电路仿真133-140&&&&&&&&5.4.1. 变频增益133-135&&&&&&&&5.4.2. 噪声系数和输入输出端口反射特性135-136&&&&&&&&5.4.3. 各个端口隔离度136-138&&&&&&&&5.4.4. 线性度138-139&&&&&&&&5.4.5. 总体性能和讨论139-140&&&&5.6 本章小结140-141&&&&参考文献141-143第六章 总结与展望143-147&&&&6.1 主要工作143-144&&&&6.2 进一步工作展望144-147致谢147-149攻读博士学位期间发表和撰写的学术论文149分享到：相关文献|}