N4030+DJ1+UMA+10212-SB
54321DDDJ1 Calpella UMA Schematics Document ArrandaleCIntel PCH
REV : X01CBBDY : Nopop ComponentA&Core Design&AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:5 4 3 2Document Number Monday, April 26, 2010Cover PageSheet1RevDJ1 Calpella UMA1 of 90X0154321DJ1 UMA Block DiagramDCPU DC/DCISL62882INPUTS+PWR_SRC47,48OUTPUTS+VCC_COREProject code : 91.4EK01.001 PCB P/N : 48.4EK19.0SB Revision : 10212-SBClock Generator SLG8SP585739SYSTEM DC/DCTPS51218INPUTS+PWR_SRC49DOUTPUTS+1.05V_VTTSYSTEM DC/DCIntel CPUDDRIII 800/1066 Channel ART8205BGQWINPUTS DDRIII 800/1066 DDRIII 800/1066 Slot 01846OUTPUTS+5V_ALW2 +3.3V_RTC_LDO +5V_ALW +3.3V_ALW +15V_ALW+PWR_SRCArrandaleDDRIII 800/1066 Channel BSlot 119SYSTEM DC/DCRT8207GQWINPUTS OUTPUTS+1.5V_SUS +0.75V_DDR_VTT +V_DDR_REF +PWR_SRC508,9,10,11,12,13,1410/100 NICPCIE x 1CATHEROS AR8152/AR8151RJ45 CONNSYSTEM DC/DCTPS51611INPUTS OUTPUTS+CPU_GFX_CORE +PWR_SRC53CCRT55RGB CRTI/O Board ConnectorDMIx4FDIx4x2(UMA)PCIE x 1Left Side: USB x 1MAXIM CHARGERBQ24745INPUTS+DC_IN +PBATT26LCD54LVDS(Dual Channel)Intel PCHCardReaderSD/MMC/MS/ MS Pro/xD71USB 2.0 x 2Mini-Card76OUTPUTS+PWR_SRCPCIE802.11a/b/gSYSTEM DC/DCAPL593051Realtek RTS513832USB2.014 USB 2.0/1.1 ports High Definition Audio SATA ports (6) PCIE ports (8) LPC I/F ACPI 1.1USB 2.0 x 1INPUTS+3.3V_ALWOUTPUTS+1.8V_RUNUSB 2.0USB 2.0 x 1CAMERA54SYSTEM DC/DCSwitches42BBBluetoothINPUTS 2673OUTPUTS+1.5V_RUN +5V_RUN +3.3V_RUNInternal Analog MICAzalia CODEC92HD79B130AZALIAPCI/PCI BRIDGEUSB 2.0 x 220,21,22,23,24,25,26,27,28+1.5V_SUS +5V_ALW +3.3V_ALWLPC BusRight Side: USB x 263PCB LAYERL1: L2: L3: L4: L5 L6: Top VCC Signal Signal GND BottomKBC SATA SATA HP1 MIC INSPISPINPCE781BA0DXNUVOTON37A2CH SPEAKER HDD59&Core Design&AODD59Flash ROM 4MB 62Flash ROM 256kB 62Touch PAD68Int. KB68ThermalEMC210239 25 TitleWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.Block DiagramDocument Number RevFan585 4 3 2Size A3 Date:DJ1 Calpella UMAMonday, April 19, 2010 Sheet1X012 of 9054321DDAdapter+PWR_SRC ISL62882 TPSmA+1.05V_VTTTPS51116 TPS51611+V_DDR_REF1000mA+0.75V_DDR_VTT16825mA+1.5V_SUSAO4407A Charger BQ24745 Battery +PBATT 48000mA+VCC_CORE22000mA+CPU_GFX_COREAOmA+1.5V_RUNCCTPSmA 82mA +15V_ALW+3.3V_RTC_LDO10330mA +5V_ALW2 +5V_ALW +3.3V_ALWG547F2P81U-GPAOmAG547F2P81U-GP 2000mA+5V_USB2AOmA+3.3V_RUNAOmA+3.3V_LANAPLmA+1.8V_RUNB2000mA+5V_USB1B+5V_RUNSI3456DDV 2000mA+LCDVDDRTSmA+3.3V_RUN_CARDPower ShapeRegulatorALDOSwitch&Core Design&AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:5 4 3 2Document Number Friday, April 16, 2010Power Block DiagramSheet1RevDJ1 Calpella UMA3 of 90X01ABCDEPCH SMBus Block Diagram+3.3V_ALW +3.3V_RUNKBC SMBus Block Diagram+5V_RUN?SRN10KJ-5-GP?+3.3V_RUN1?SRN2K2J-1-GP SRN2K2J-1-GP? ?PCH_SMBCLK ? PCH_SMBDATADMN66D0LDW-7-GPTouchPad Conn. DIMM 1SCL SDA +KBC_PWR181PSDAT1 PSCLK1TPDATA TPCLKSMBCLK SMBDATAPCH_SMB_CLKPCH_SMB_DATA? ?? ?TPDATA TPCLKTPDATA TPCLK?SMBus Address:A0DIMM 2?PCH_SMBCLK ? PCH_SMBDATASCL SDA19SRN4K7J-8-GPSRN100J-3-GP SCL1 BAT_SCL BAT_SDA PBAT_SMBCLK1 PBAT_SMBDAT1 SDA1Battery Conn.CLK_SMB DAT_SMBSMBus Address:A4SMBus address:16?PCH_SMBCLK ? PCH_SMBDATAClock GeneratorSCLK SDATA7KBCNPCE781BA0DXBQ24745SCL SDASMBus address:12SMBus address:D22+3.3V_RUN2PCH+3.3V_ALW??PCH_SMBCLK ? PCH_SMBDATASRN2K2J-1-GPMinicard WLANSMB_CLK SMB_DATA76?+3.3V_ALW +3.3V_RUN SRN4K7J-8-GP?SRN4K7J-8-GP? ? ?THERM_SCL THERM_SDA SCL SDAThermalSMBus address:7ASML0CLK SML0DATASML0_CLK SML0_DATA? ?+3.3V_RUNXDPGPIO61/SCL2 GPIO62/SDA2KBC_SCL1 DMN66D0LDW-7-GP KBC_SDA1?SRN2K2J-1-GPPCHSML1DATA/GPIO75 SML1CLK/GPIO58L_DDC_CLK L_DDC_DATA3LDDC_CLK LDDC_DATA? ?LCD CONN233+3.3V_RUN+5V_CRT_RUN?+3.3V_RUN SRN2K2J-1-GP?SRN2K2J-1-GP?CRT_DDC_CLK CRT_DDC_DATA GMCH_DDCCLK GMCH_DDCDATA? ?DMN66D0LDW-7-GP? ?DDC_CLK_CON DDC_DATA_CONCRT CONN2344&Core Design&Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A2 Date:A B C DDocument Number Friday, April 16, 2010SMBUS Block DiagramSheetERevDJ1 Calpella UMA4 of 90X01ABCDEThermal Block Diagram1Audio Block Diagram1SPKR_PORT_D_LSPKR_PORT_D_R+SPEAKERCodec ALC269Q_VB5DP1 EMC2102_DP1 MMBT3904-3-GP SC470P50V3JN-2GP2HP1_PORT_B_L HP1_PORT_B_RDN1EMC2102_DN1HP OUT2Thermal EMC2102DP2 EMC2102_DP1Place near CPU and PCH.HP0_PORT_A_L MMBT3904-3-GP HP0_PORT_A_R DN2 EMC2102_DN1 VREFOUT_A_OR_FMIC INSystem Sensor(UMA only)33DP3EMC2102_DP3 MMBT3904-3-GP SC470P50V3JN-2GPDN3EMC2102_DN3Put under CPU.PORTC_L PORTC_R VREFOUT_CAnalog MIC4&Core Design&4Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document Number Custom Date:A B C DThermal/Audio Block DiagramDJ1 Calpella UMASheetERevX015 of 90Friday, April 16, 2010ABCDEPCH StrappingNameSPKRProcessor StrappingCalpella Schematic Checklist Rev.0_7 Schematics Notes Calpella Schematic Checklist Rev.0_7Pin NameCFG[4]Strap DescriptionEmbedded DisplayPort Presence PCI-Express Static Lane Reversal PCI-Express Configuration Select Reserved Temporarily used for early Clarksfield samples.4INIT3_3V# GNT3#/ GPIO55 INTVRMEN GNT0#, GNT1#/GPIO51Reboot option at power-up Default Mode: Internal weak Pull-down. No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k- 10-k? weak pull-up resistor. Weak internal pull-down. Do not pull high. Default Mode: Internal pull-up. Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak pull-down resistor). High (1) = Integrated VRM is enabled Low (0) = Integrated VRM is disabled Default (SPI): Left both GNT0# and GNT1# floating. No pull up required. Boot from PCI: Connect GNT1# to ground with 1-k pull-down resistor. Leave GNT0# Floating. Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k pull-down resistor. Default - Internal pull-up. Low (0)= Configures DMI for ESI compatible operation (for servers only. Not for mobile/desktops). Default: Do not pull low. Disable ME in Manufacturing Mode: Connect to ground with 1-k? pull-down resistor. Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull- up resistor. Left floating, no pull-down required. Disable iTPM: Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Disable Danbury: Connect to ground with 4.7-k? weak pull-down resistor. Weak internal pull-up. Do not pull low. Low (0): Flash Descriptor Security will be overridden. High (1) : Flash Descriptor Security will be in effect. Weak internal pull-down. Do not pull high. Weak internal pull-down. Do not pull high. Weak internal pull-down. Do not pull high. Weak internal pull-up. Do not pull low. Default = Do not connect (floating) High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.Configuration (Default value for each bit is 1 unless specified otherwise)1: Disabled - No Physical Display Port attached to Embedded DisplayPort. 0: Enabled - An external Display Port device is connected to the Embedded Display Port. 1: Normal Operation. 0: Lane Numbers Reversed 15 -& 0, 14 -& 1, ... 1: Single PCI-Express Graphics 0: Bifurcation enabled Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor Note: Only temporary for early CFD samples (rPGA/BGA) [For details please refer to the WW33 MoW and sighting report]. For a common motherboard design (for AUB and CFD), the pull-down resistor should be used. Does not impact AUB functionality.Default Value141CFG[3]CFG[0]1CFG[7]0GNT2#/ GPIO53 GPIO333SPI_MOSI NV_ALE3NC_CLE HAD_DOCK_EN# /GPIO[33] HDA_SDO HDA_SYNC GPIO15 GPIO8 GPIO2722PCIE RoutingLANE2 LANE3 MiniCard WLAN LANUSB TableUSB Pair 0 1 2 3 4 5 6 7 8 9 10 11 12 13 X USB2 USB3 X WLAN (I/O Board) X X X BLUETOOTH CARD READER CAMERA X XTitle Size A3 Date: Document Number Friday, April 16, 2010 &Core Design&Device USB0 (I/O Board)11Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.Table of ContentSheet 6 ofRevDJ1 Calpella UMA90X01ABCDE54321SSID = CLOCK+3.3V_RUN +3.3V_RUN_SL585D+1.05V_VTT+1.05V_RUN_SL585_IOD1 R708 2 0R0603-PAD-1-GP 1 1 1 1 1 1 1C701 SC1U10V2KX-1GP C702 SC10U10V5ZY-1GP C703 SCD1U16V2ZY-2GP C704 SCD1U16V2ZY-2GP C705 SCD1U16V2ZY-2GP C707 SCD1U16V2ZY-2GP11 R709 2 0R0603-PAD-1-GP 1 1C709 SCD1U16V2ZY-2GP C710 SC10U10V5ZY-1GP C711 SCD1U16V2ZY-2GP1 2C708 SC1U10V2KX-1GP2222222DYDYC712 SCD1U16V2ZY-2GP22+3.3V_RUN_SL585 +3.3V_RUN R701+1.05V_RUN_SL585_IO12CPU_STOP#2K2R2J-2-GP24172915U701VDD_SRC_IO23 23 23 23DREFCLK# DREFCLK CLKIN_DMI# CLKIN_DMI23 CLK_PCIE_SATA# 23 CLK_PCIE_SATA 23 CLK_CPU_BCLK# 23 CLK_CPU_BCLK19 20CPU_1# CPU_1 VSS_SATA VSS_CPU VSS_SRC VSS_DOT VSS_REF VSS_27SDA SCL31 32PCH_SMBDATA PCH_SMBCLKBGNDPCH_SMBDATA 18,19,23,76 PCH_SMBCLK 18,19,23,76B28332621FSC+1.05V_VTT X701 CLK_XTAL_IN129SLG8SP585VTR-GP0 133MHz (Default)1 100MHz+3.3V_RUN_SL5851 12CLK_XTAL_OUTSPEED2R704C714 SC12P50V2JN-3GPAX-14D31818M-37GP12282.2C715 SC12P50V2JN-3GPDY 4K7R2J-2-GP1FSC R705 10KR2J-3-GP22 0R4P2R-PAD 1 RN701 2 0R4P2R-PAD 1 RN702 2 0R4P2R-PAD 1 RN703 1 0R4P2R-PAD 2 RN7043 4 3 4 3 4 4 3RNCLK_MCH_DREFCLK1# CLK_MCH_DREFCLK1 CLK_IN_DMI# CLK_IN_DMI CLK_PCIE_SATA1# CLK_PCIE_SATA1 CLK_CPU_BCLK1# CLK_CPU_BCLK14 3 14 13 11 10 22 23VDD_CPU_IOVDD_CPUVDD_SRCVDD_REFVDD_DOTVDD_271815C2DYCDOT_96# DOT_96 SRC_2# SRC_2 SRC_1/SATA# SRC_1/SATA CPU_0# CPU_027MHZ 27MHZ_SS CPU_STOP# CKPWRGD/PD# REF_0/CPU_SEL XTAL_IN XTAL_OUT6 7 16 25 30 28 27CPU_STOP# CK_PW RGD FSC CLK_XTAL_IN CLK_XTAL_OUT21R703 33R2J-2-GP EC701 SC4D7P50V2CN-1GPCLK_PCH_14M2311. . . .2R707 10KR2J-3-GP.1RN RN RNDY&Core Design&AGVR_CLKEN#47Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date: Document NumberCK_PW RGDDSQ701 2N7002E-1-GPClock Generator SLG8SP585DJ1 Calpella UMASheet1RevX017 of 90Thursday, April 22, 20105432SSID = CPU54321DMain:62.nd :62.rd :62.CPU1A 1 OF 9PEG_IRCOMP_R EXP_RBIASR801 1 R802 12 49D9R2F-GP 2 750R2F-GPDDMI_RX0# DMI_RX1# DMI_RX2# DMI_RX3# DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 DMI_TX0# DMI_TX1# DMI_TX2# DMI_TX3# DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3AUBURNDALE22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22DMI_PTX_CRXN0 DMI_PTX_CRXN1 DMI_PTX_CRXN2 DMI_PTX_CRXN3 DMI_PTX_CRXP0 DMI_PTX_CRXP1 DMI_PTX_CRXP2 DMI_PTX_CRXP3 DMI_CTX_PRXN0 DMI_CTX_PRXN1 DMI_CTX_PRXN2 DMI_CTX_PRXN3 DMI_CTX_PRXP0 DMI_CTX_PRXP1 DMI_CTX_PRXP2 DMI_CTX_PRXP3A24 C23 B22 A21 B24 D23 B23 A22 D24 G24 F23 H23 D25 F24 E23 G23PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS PEG_RX0# PEG_RX1# PEG_RX2# PEG_RX3# PEG_RX4# PEG_RX5# PEG_RX6# PEG_RX7# PEG_RX8# PEG_RX9# PEG_RX10# PEG_RX11# PEG_RX12# PEG_RX13# PEG_RX14# PEG_RX15# PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15B26 A26 B27 A25 K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25DMIC22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1E22 D21 D19 D18 G21 E19 F21 G18 D22 C21 D20 C18 G22 E20 F20 G19 F17 E17 C17 F18 D17FDI_TX0# FDI_TX1# FDI_TX2# FDI_TX3# FDI_TX4# FDI_TX5# FDI_TX6# FDI_TX7# FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7 FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1CIntel(R) FDIPCI EXPRESS -- GRAPHICSBPEG_TX0# PEG_TX1# PEG_TX2# PEG_TX3# PEG_TX4# PEG_TX5# PEG_TX6# PEG_TX7# PEG_TX8# PEG_TX9# PEG_TX10# PEG_TX11# PEG_TX12# PEG_TX13# PEG_TX14# PEG_TX15# PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15BA&Core Design&AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date: Document NumberCPU (PCIE/DMI/FDI)Sheet 8 ofRevDJ1 Calpella UMAThursday, April 22, 2010 90X01543215+1.05V_VTT4Processor Compensation SignalsCPU1BSSID = CPURN 2 OF 93211DDR_RST_GATE C915 SCD047U16V2ZY-1GP +1.5V_SUS 25Processor PullupsR9011 1R903220R2F-GPH_COMP3 H_COMP2 20R2F-GP H_COMP1 49D9R2F-GP H_COMP0 49D9R2F-GP SKTOCC#_R H_CATERR#AT23 AT24 G16 AT26 AH24 AK14COMP3AUBURNDALECOMP2 COMP1 COMP0 SKTOCC# CATERR#CLOCKSR933 1 R904 12 68R2-GPH_PROCHOT# H_CPURST#R9051R9062 1BCLK_ITP BCLK_ITP# PEG_CLK PEG_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#1 4 RN903 3 0R4P2R-PADQ901 CLK_EXP_P 23 CLK_EXP_N 23 R934 1KR2J-1-GP12AR30 AT30 E16 D16 A18 A17BCLK_ITP_P BCLK_ITP_N PEG_CLK_R PEG_CLK#_RDD 12DY2 68R2-GP1 2G2R902 12 49D9R2F-GPH_CATERR#2BCLK BCLK#A16 B16BCLK_CPU_P_R BCLK_CPU_N_R1 2RN4 RN901 3 0R4P2R-PADBCLK_CPU_P BCLK_CPU_N25 25MISC. . . .TPAD14-GPTP901DDR3_DRAMRST#18,19D.S F6 AL1 AM1 AN1 AN15 AP15SM_DRAMRST# RN905 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 PM_EXTTS#0_C PM_EXTTS#1_C 0R4P2R-PAD RN906 XDP_PRDY# XDP_PREQ# XDP_TCLK XDP_TMS XDP_TRST# XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M H_DBR#_R XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 XDP_TMS PM_EXTTS#0_C 53 +1.05V_VTT 2N7002E-1-GPTHERMAL25 H_PECIAT15SM_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 PM_EXT_TS0# PM_EXT_TS1#PECI4 31 21 R935DY2 0R2J-2-GP47 H_PROCHOT#AN26PROCHOT#SRN10KJ-5-GP 1 4 2 3PM_EXTTS#0 18 PM_EXTTS#1 1925,37,42 H_THERMTRIP#AK15THERMTRIP#DDR3 MISCSM_DRAMRST#2C903 SCD1U10V2KX-5GPRN12PRDY# PREQ# TCK TMS TRST# TDI TDO TDI_M TDO_M DBR# BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPM6# BPM7#AT28 AP27 AN28 AP28 AT27 AT29 AR27 AR29 AP29 AN25 AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23R988 100KR2J-1-GPH_CPURST#AP26 AL15 AN14RESET_OBS# PM_SYNC VCCPWRGOOD_1 VCCPWRGOOD_0 SM_DRAMPWROK VTTPWRGOOD TAPPWRGOOD RSTIN#PWR MANAGEMENT22 H_PM_SYNCJTAG & BPMDDR3 Compensation SignalsSM_RCOMP_0 R907 1 R910 1 R911 1C25,42 H_PW RGD2 100R2F-L1-GP-U 2 24D9R2F-L-GP 2 130R2F-1-GP1 R908 2 0R0402-PAD 1 R912 2 0R0402-PADVCCPW RGOOD VDDPW RGOOD_R1 R9092XDP_DBRESET#SM_RCOMP_1 SM_RCOMP_2CAN27 AK13 AM150R0402-PAD22 PM_DRAM_PW RGD 49 H_VTTPW RGD H_PW RGD_XDPAM26R913+1.05V_VTT21,37,70,76PLT_RST#12 11K6R2F-GPPLT_RST#_RAL141R914XDP_TDI_R R915 750R2F-GP R916 +3.3V_RUN XDP_PREQ# R917 XDP_TCLK R9181 1 1DY DY DY DY251R2J-2-GP251R2J-2-GP251R2J-2-GP1119S3 circuitR919 NormalR9202251R2J-2-GP1.1k 0.75k No Stuff 1.27k 3k1 2 3U927B VCC A Y GNDB+1.5V_RUN XDP15 4VTT_PW RGD_R3R97737,42,49 VTT_PW RGD12VDDPW RGOOD_R XDP_TDI_RBXDP_TDO_MR978 37 VDDPW RGOOD_KBC21DYVDDPW RGOOD_RR919 1K1R2F-GP XDP_PREQ# XDP_PRDY# XDP_OBS0 XDP_OBS11 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59R937 750R2F-GPXDP_OBS2 XDP_OBS3XDP_OBS4 XDP_OBS5 +1.05V_VTT H_PW RGD 22 PM_PW RBTN#_R H_PW RGD_XDP XDP_OBS6 XDP_OBS7DY1 R927 1 R929 1 R930DY DY DYH_CPUPW RGD_XDP 2 2 1KR2J-1-GP PM_PW RBTN#_XDP 0R2J-2-GP PCIE_CLK_XDP_P 2 0R2J-2-GPA2DYC902 SCD1U16V2KX-3GP23 SML0_DATA 23 SML0_CLK XDP_TCLKNP1 61 2 62 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 63 64 NP274LVC1G08GW -1-GP1 R922DY20R2J-2-GPXDP_TDO1R923 51R2J-2-GP1K6R2F-GP1 R921DY120R2J-2-GPXDP_TDIXDP_TRST#11DY2XDP_TDI_M XDP_TDO_RR924 0R0402-PAD21K6R2F-GP1 R925DY20R2J-2-GP2+1.05V_VTT1 R92620R0402-PADBCLK_ITP_P BCLK_ITP_N XDP_RST#_R R931 XDP_TRST# XDP_TDI XDP_TMS21C901 SCD1U16V2KX-3GPDYScan Chain (Default) CPU OnlyR928 51R2J-2-GPGMCH OnlyXDP_DBRESET# 22Stuff --& R921, R924, R926 No Stuff --& R922, R925 Stuff --& R921, R922 No Stuff --& R924, R926, R925 Stuff --& R926, R925 No Stuff --& R921, R922, R924&Core Design&JTAG MAPPING21DY2 1KR2J-1-GPH_CPURST#12XDP_TDOA1Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. XDP_RST#_R1 R9322 DY0R2J-2-GPPLT_RST# 21,37,70,76Title Size Date: Document NumberCPU (THERMAL/CLOCK/PM )DJ1 Calpella UMASheet 9 ofPAD-60P-GPRevX0190Thursday, April 22, 20105432154321SSID = CPUCPU1C 3 OF 9CPU1D4OF 9AUBURNDALEAUBURNDALE18 M_A_DQ[63..0]DM_A_DQ[63..0] M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63CBA10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14SA_CK0 SA_CK0# SA_CKE0AA6 AA7 P719 M_B_DQ[63..0] M_CLK_DDR0 18 M_CLK_DDR#0 18 M_CKE0 18M_B_DQ[63..0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63SA_CK1 SA_CK1# SA_CKE1Y6 Y5 P6M_CLK_DDR1 18 M_CLK_DDR#1 18 M_CKE1 18SA_CS0# SA_CS1#AE2 AE8M_CS#0 18 M_CS#1 18SA_ODT0 SA_ODT1AD8 AF9M_ODT0 18 M_ODT1 18SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7B9 D7 H7 M7 AG6 AM7 AN10 AN13M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7M_A_DM[7..0]18 18 18 18M_A_DQS#[7..0] M_A_DQS[7..0]DDR SYSTEM MEMORY ADDR SYSTEM MEMORY - BSA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#C9 F8 J9 N9 AH7 AK9 AP11 AT13M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7M_A_A[15..0]SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7C8 F9 H9 M9 AH8 AK10 AN11 AR13M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS718 18 18M_A_BS0 M_A_BS1 M_A_BS2AC3 AB2 U7SA_BS0 SA_BS1 SA_BS218 18 18M_A_CAS# M_A_RAS# M_A_W E#AE1 AB3 AE9SA_CAS# SA_RAS# SA_WE#SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63SB_CK0 SB_CK0# SB_CKE0 SB_CK1 SB_CK1# SB_CKE1W8 W9 M3 V7 V6 M2M_CLK_DDR2 19 M_CLK_DDR#2 19 M_CKE2 19 M_CLK_DDR3 19 M_CLK_DDR#3 19 M_CKE3 19DSB_CS0# SB_CS1#AB8 AD6M_CS#2 19 M_CS#3 19SB_ODT0 SB_ODT1AC7 AD1M_ODT2 19 M_ODT3 19SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7D4 E1 H3 K1 AH1 AL2 AR4 AT8M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7M_B_DM[7..0]19 19 19 19CM_B_DQS#[7..0] M_B_DQS[7..0]SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#D5 F4 J4 L4 AH2 AL4 AR5 AR8M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7M_B_A[15..0]SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7C5 E3 H4 M5 AG2 AL5 AP5 AR7M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7B19 19 19 19 19 19M_B_BS0 M_B_BS1 M_B_BS2 M_B_CAS# M_B_RAS# M_B_W E#AB1 W5 R7 AC5 Y7 AC6SB_BS0 SB_BS1 SB_BS2 SB_CAS# SB_RAS# SB_WE#SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15A&Core Design&AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:5 4 3 2Document Number Thursday, April 22, 2010CPU (DDR)Sheet1RevDJ1 Calpella UMA10 of 90X0154321SSID = CPUCPU1E5OF 9 AJ13 AJ12 AH25 AK26 AL26 AR2 AJ26 AJ27AUBURNDALEDRSVD#AJ13 RSVD#AJ12 RSVD#AH25 RSVD#AK26 RSVD#AL26 RSVD_NCTF#AR2 RSVD#AJ26 RSVD#AJ27DCFG0PCI-Express Configuration SelectRF-GPTP1116 TP11171 1SA_DIMM_VREF# SB_DIMM_VREF#DY2CFG01:Single PEG 0:Bifurcation enabledAP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30RSVD#AP25 RSVD#AL25 RSVD#AL24 RSVD#AL22 RSVD#AJ33 RSVD#AG9 RSVD#M27 RSVD#L28 SA_DIMM_VREF# SB_DIMM_VREF# RSVD#G25 RSVD#G17 RSVD#E31 RSVD#E301CFG0 CFG3 CFG4CFG3CFG3 - PCI-Express Static Lane ReversalRJ-2-GP CFG7CRESERVEDDY2CFG31 :Normal Operation 0 :Lane Numbers Reversed 15 -& 0, 14 -& 1, ...AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 RSVD_TP#H16RSVD#AL28 RSVD#AL29 RSVD#AP30 RSVD#AP32 RSVD#AL27 RSVD#AT31 RSVD#AT32 RSVD#AP33 RSVD#AR33AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR331CRSVD#AR32 RSVD_TP#E15 RSVD_TP#F15 KEY RSVD#D15 RSVD#C15 RSVD#AJ15 RSVD#AH15AR32 E15 F15 A2 D15 C15 AJ15 AH15CFG4CFG4 - Display Port PresenceRF-GPB19 A19 A20 B20 U9 T9 AC9 AB9RSVD#B19 RSVD#A19 RSVD#A20 RSVD#B20 RSVD#U9 RSVD#T9 RSVD#AC9 RSVD#AB9 RSVD_TP#AA5 RSVD_TP#AA4 RSVD_TP#R8 RSVD_TP#AD3 RSVD_TP#AD2 RSVD_TP#AA2 RSVD_TP#AA1 RSVD_TP#R9 RSVD_TP#AG7 RSVD_TP#AE3 RSVD_TP#V4 RSVD_TP#V5 RSVD_TP#N2 RSVD_TP#AD5 RSVD_TP#AD7 RSVD_TP#W3 RSVD_TP#W2 RSVD_TP#N3 RSVD_TP#AE5 RSVD_TP#AD9 VSS1DY2CFG41:D No Physical Display Port attached to Embedded Display Port 0:E An external Display Port device is connected to the Embedded Display PortAA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 AP34CFG7 RF-GPBCFG7(Reserved) - Temporarily used for early Clarksfield samples. CFG7 Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor. Note: Only temporary for early CFD sample (rPGA/BGA) [For details please refer to the WW33 MoW and sighting report]. For a common M/B design (for AUB and CFD), the pull-down resistor shouble be used. Does not impact AUB functionality.1DY2J29 J28RSVD#J29 RSVD#J28VSS (AP34) can be left NC is CRB EDS/DG recommendation to GND.BAA&Core Design&Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:5 4 3 2Document Number Friday, April 16, 2010CPU (RESERVED)Sheet1RevDJ1 Calpella UMA11 of 90X0154321SSID = CPU+VCC_CORECPU1F6OF 9AUBURNDALE+1.05V_VTT VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11PROCESSOR CORE POWER+VCC_CORED48A1 1 1 1 1 C1206 SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP SC10U6D3V5KX-1GP C1207 SC10U6D3V5KX-1GP C1208 SC10U6D3V5KX-1GP C1209 SC10U6D3V5KX-1GP C1220 SC10U6D3V5KX-1GP C1210 SC10U6D3V5KX-1GPDY2DY2DY222111111DY2DY222221111111C1225C1226 SC10U6D3V5MX-3GPC1227 SC10U6D3V5KX-1GPC1229 SC10U6D3V5MX-3GPC1230 SC10U6D3V5KX-1GPC1231 SC10U6D3V5MX-3GPC1232 SC10U6D3V5KX-1GP2222222DYC1111111C1235 SC10U6D3V5KX-1GPC1236 SC10U6D3V5KX-1GPC1237 SC10U6D3V5KX-1GPC1238 SC10U6D3V5KX-1GPC1240 SC10U6D3V5KX-1GPC1241 SC10U6D3V5MX-3GPC1242 SC10U6D3V5KX-1GPVTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J151C1233 SC10U6D3V5KX-1GP1C1234CDY2DY2DY22222222C1212C1213 SC10U6D3V5KX-1GPC1214 SC10U6D3V5KX-1GPC1215 SC10U6D3V5KX-1GPC1223 SC10U6D3V5KX-1GPC1224 SC10U6D3V5KX-1GP1C1243 SC10U6D3V5KX-1GP X01BAG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC11111111C1216 SC10U6D3V5KX-1GPC1201 SC10U6D3V5KX-1GPC1202 SC10U6D3V5KX-1GPC1217 SC10U6D3V5KX-1GPC1218 SC10U6D3V5KX-1GPC1203 SC10U10V5ZY-1GPC1219 SC10U10V5ZY-1GPC1204 SC10U10V5ZY-1GPC1205 SC10U6D3V5KX-1GP222222222DYDYDY1D1222+1.05V_VTT11C1211 SC10U6D3V5KX-1GPC1221 SC10U6D3V5KX-1GP1C1222 SC10U6D3V5MX-3GP1.1V RAIL POWERDYThe decoupling capacitors, filter recommendations and sense resistors on the CPU/PCH Rails are specific to the CRB Implementation. Customers need to follow the recommendations in the Calpella Platform Design Guide.+1.05V_VTTCPU CORE SUPPLYSC10U6D3V5MX-3GPPlease note that the VTT Rail Values are Auburndale VTT=1.05V; Clarksfield VTT=1.1VPSI# VID0 VID1 VID2 VID3 VID4 VID5 VID6 PROC_DPRSLPVR AN33 AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PSI# 47 472H_VID[6..0]POWERCPU VIDSPM_DPRSLPVR 47BVTT_SELECTG15H_VTTVID11TP1201 TPAD14-GPH_VTTVID1 = Low, 1.1V H_VTTVID1 = High, 1.05V+VCC_CORE 1ISENSEAN35IMVP_IMON 47RF-L1-GP-U 2SENSE LINESVCC_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTTAJ34 AJ35 1 B15 A15 RF-L1-GP-U 2VCC_SENSE 47 VSS_SENSE 47 VTT_SENSE 49 TP1202 TPAD14-GPTP_VSS_SENSE_VTT 1AA&Core Design&Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Document NumberCPU (VCC_CORE)Sheet1RevDJ1 Calpella UMADate: Thursday, April 22, 20105 4 3 2X0112 of 9054321SSID = CPU+CPU_GFX_CORE+1.5V_RUN+1.5V_RUN+1.5V_RUN+1.5V_RUN111DYC13762SCD1U10V2KX-4GP +1.5V_SUSDYC13772SCD1U10V2KX-4GP +1.5V_SUSDYC13782SCD1U10V2KX-4GP +1.5V_SUSDYC1379+1.5V_SUS122ADCPU1G7OF 9 X012222222SENSE LINES1111111C1325 SC10U6D3V5MX-3GPC1328 SC10U6D3V5MX-3GPC1323 SC10U6D3V5MX-3GPC1326C1324C1309C1312- 1.5V RAILSPlease note that the VTT Rail Values are: Auburndale VTT=1.05V Clarksfield VTT=1.1VCAT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16302_Calpella_S3PowerReduction_WhitePapeVAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36AUBURNDALEVAXG_SENSE VSSAXG_SENSEAR22 AT22VCC_AXG_SENSE 53 VSS_AXG_SENSE 53Revision 0.72SCD1U10V2KX-4GPDGRAPHICS VIDs1111111C1301 SC1U6D3V2KX-GPC1302 SC1U6D3V2KX-GPC1303 SC1U6D3V2KX-GPC1304 SC1U6D3V2KX-GPC1305 SC1U6D3V2KX-GPC1306 SC10U6D3V5MX-3GPC1307 SC10U6D3V5MX-3GPDY212222222+1.05V_VTTPOWER1C1308 SC10U6D3V5KX-1GPJ24 J23 H25VTT1 VTT1 VTT1DDR3211SC10U6D3V5MX-3GPSC10U6D3V5MX-3GPSC10U6D3V5MX-3GPSC10U6D3V5MX-3GPGFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6 GFX_VR_EN GFX_DPRSLPVR GFX_IMONAM22 AP22 AN22 AP23 AM23 AP24 AN24R1305GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID653 53 53 53 53 53 53GRAPHICSFDI2 1 R13041 4K7R2J-2-GPAR25 AT25 AM24GFX_IMON_CDY2 0R2J-2-GPGFX_VR_EN 53 GFX_DPRSLPVR 53 GFX_IMON 53VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQAJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H13A+1.5V_RUNTC1301 SE330U2D5VDM-2GPCVTT1 VTT1 VTT1 VTT1P10 N10 L10 K10C1310 SC10U6D3V5KX-1GP C1311 SC10U6D3V5KX-1GP+1.05V_VTT21.1V11BC1314 SC10U10V5KX-2GP1C1313 SC10U6D3V5KX-1GPC1315 SC10U6D3V5KX-1GPDY21.8VK26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1VTT1 VTT1 VTT1 VTT1 VTT1 VTT1J22 J20 J18 H21 H20 H19 1C1316 SC10U6D3V5KX-1GP2+1.05V_VTT18A+1.05V_VTTBPEG & DMI221 2VTT1 VTT1 VTT1L26 L27 M262DYC1317 SC10U6D3V5MX-3GP1.35A1 1 1 1C1319 SC1U6D3V2KX-GP C1320 SC4D7U6D3V5KX-3GP C1321 SC2D2U6D3V3KX-GP+1.8V_RUNC1318 SC1U6D3V2KX-GP1 2C1322 SC10U6D3V5MX-3GP &Core Design&222A2AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size Date:5 4 3 2Document NumberCPU (VCC_GFXCORE)DJ1 Calpella UMASheet1RevX0113 of 90Thursday, April 22, 201054321SSID = CPUCPU1H 8 OF 9 CPU1I 9 OF 9DCBAT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSVSSVSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSAE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30AUBURNDALEK27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSSAUBURNDALEDCVSSAR34 B34 B2 B1 A35 AT1 AT35 AT33 AT34 AP35 AR35 AT3 AR1 AP1 AT2 C1 A3 C35 B35 A34 A33TP_MCP_VSS_NCTF1 TP_MCP_VSS_NCTF2 TP_MCP_VSS_NCTF3 TP_MCP_VSS_NCTF4NCTF TEST PIN: A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35, AR1,AR35,AT2,AT3,AT33,AT34,B35,C1,C35VSS_NCTF#AR34 VSS_NCTF#B34 VSS_NCTF#B2 VSS_NCTF#B1 VSS_NCTF#A35 VSS_NCTF#AT1 VSS_NCTF#AT35 RSVD_NCTF#AT33 RSVD_NCTF#AT34 RSVD_NCTF#AP35 RSVD_NCTF#AR35 RSVD_NCTF#AT3 RSVD_NCTF#AR1 RSVD_NCTF#AP1 RSVD_NCTF#AT2 RSVD_NCTF#C1 RSVD_NCTF#A3 RSVD_NCTF#C35 RSVD_NCTF#B35 RSVD_NCTF#A34 RSVD_NCTF#A331 1 1 1TP1403 TP1404 TP1406 TP1405BA&Core Design&AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. TitleCPU (VSS)Size Date:5 4 3 2Document NumberRevDJ1 Calpella UMAFriday, April 16, 2010 Sheet1X0114 of 9054321DDCC(Blanking)BBA&Core Design&AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:5 4 3 2Document Number Friday, April 16, 2010ReservedSheet1RevDJ1 Calpella UMA15 of 90X0154321DDCC(Blanking)BBA&Core Design&AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:5 4 3 2Document Number Friday, April 16, 2010ReservedSheet1RevDJ1 Calpella UMA16 of 90X0154321DDCC(Blanking)BBA&Core Design&AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title Size A3 Date:5 4 3 2Document Number Friday, April 16, 2010ReservedSheet1RevDJ1 Calpella UMA17 of 90X0154321SSID = MEMORYDM1 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 10 M_A_BS2 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 109 108 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 10 10 M_ODT0 M_ODT1 +V_DDR_REF C1820 SC1U6D3V2KX-GP C1821 SC1U6D3V2KX-GP C1822 SC1U6D3V2KX-GP C1823 SC1U6D3V2KX-GP 1 1 1 1 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 10 27 45 62 135 152 169 186 12 29 47 64 137 154 171 188 116 120 126 1 30 203 204 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2 NP1 NP2 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL EVENT# VDDSPD SA0 SA1 NC#1 NC#2 NC#/TEST VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NP1 NP2 110 113 115 114 121 73 74 101 103 102 104 11 28 46 63 136 153 170 187 200 202 198 199 197 201 77 122 125 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 SA0_DIM0 SA1_DIM0 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 SODIMM0_1_SMB_DATA_R SODIMM0_1_SMB_CLK_RM_A_DM[7..0] 10 M_A_DQS#[7..0] M_A_DQS[7..0] 10 10M_A_A[15..0] 10M_A_RAS# 10 M_A_WE# 10 M_A_CAS# 10 M_CS#0 10 M_CS#1 10 M_CKE0 10 M_CKE1 10 M_CLK_DDR0 10 M_CLK_DDR#0 10 M_CLK_DDR1 10 M_CLK_DDR#1 10SA0_DIM0 SA1_DIM0 3 4Note: If SA0 DIM0 = 0, SA1_DIM0 = 0 SO-DIMMA SPD Address is 0xA0 SO-DIMMA TS Address is 0x30RN1801 SO-DIMMA SRN10KJ-5-GPDIf SA0 DIM0 = 1, SA1_DIM0 = 0 SPD Address is 0xA2 SO-DIMMA TS Address is 0x32D10 M_A_BS0 10 M_A_BS1 10 M_A_DQ[63..0]R1 12 0R0402-PAD 2 0R0402-PADPM_EXTTS#0 9PCH_SMBDATA 7,19,23,76 PCH_SMBCLK 7,19,23,76 +3.3V_RUN12+1.5V_SUS2C1801 SCD1U10V2KX-5GP1DYC1802 SC2D2U10V3KX-1GP2 1SODIMM A DECOUPLING+1.5V_SUSCC11111111DY22222222+V_DDR_REF11222C1817 SCD1U10V2KX-5GPDYC1818 SC2D2U10V3KX-1GP1C1826 SCD1U10V2KX-5GPC1813 SCD1U10V2KX-5GP 2 1C1814 SCD1U10V2KX-5GP 2 1C1815 SCD1U10V2KX-5GP 2 1Layout Note: Place these Caps near SO-DIMMA.BC1816 SCD1U10V2KX-5GP212DYDYDYDYDY1TC1801 SE330U2D5VDM-2GPC1803 SC10U10V5ZY-1GPC1804 SC10U10V5ZY-1GPC1805 SC10U6D3V5KX-1GPC1806 SC10U10V5ZY-1GPC1807 SC10U6D3V5KX-1GPC1808 SC10U6D3V5KX-1GPC1809 SC10U6D3V5KX-1GPC1810 SC10U6D3V5KX-1GPB+0.75V_DDR_VTTPlace these caps close to VTT1 and VTT2.2222DYDY9,19 DDR3_DRAMRST# +0.75V_DDR_VTTH =5.2mmDDR3-204P-46-GP62.10017.P11AA&Core Design&Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. TitleDDR3-SODIMM1Size Date:5 4 3 2Document NumberRevDJ1 Calpella UMAThursday, April 22, 20101X0118 of 90Sheet54321SSID = MEMORYM_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15DDM2 98 97 96 95 92 91 90 86 89 85 107 84 83 119 80 78 79 109 108 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 10 10 M_ODT2 M_ODT3 +V_DDR_REF +0.75V_DDR_VTT 5 7 15 17 4 6 16 18 21 23 33 35 22 24 34 36 39 41 51 53 40 42 50 52 57 59 67 69 56 58 68 70 129 131 141 143 130 132 140 142 147 149 157 159 146 148 158 160 163 165 175 177 164 166 174 176 181 183 191 193 180 182 192 194 10 27 45 62 135 152 169 186 12 29 47 64 137 154 171 188 116 120 126 1 30 203 204 C1919 SC1U6D3V2KX-GP C1920 SC1U6D3V2KX-GP C1921 SC1U6D3V2KX-GP C1922 SC1U6D3V2KX-GP A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15 A16/BA2 BA0 BA1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 ODT0 ODT1 VREF_CA VREF_DQ RESET# VTT1 VTT2 NP1 NP2 RAS# WE# CAS# CS0# CS1# CKE0 CKE1 CK0 CK0# CK1 CK1# DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 SDA SCL EVENT# VDDSPD SA0 SA1 NC#1 NC#2 NC#/TEST VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NP1 NP2 110 113 115 114 121 73 74 101 103 102 104 11 28 46 63 136 153 170 187 200 202 198 199 1 197 201 77 122 125 75 76 81 82 87 88 93 94 99 100 105 106 111 112 117 118 123 124 2 3 8 9 13 14 19 20 25 26 31 32 37 38 43 44 48 49 54 55 60 61 65 66 71 72 127 128 133 134 138 139 144 145 150 151 155 156 161 162 167 168 172 173 178 179 184 185 189 190 195 196 205 206 SA0_DIM1 SA1_DIM1 C1901 SCD1U10V2KX-5GP +1.5V_SUS 1 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SODIMM1_1_SMB_DATA_R SODIMM1_1_SMB_CLK_R R 1 1 2 0R0402-PAD 2 0R0402-PAD PCH_SMBDATA 7,18,23,76 PCH_SMBCLK 7,18,23,76 +3.3V_RUN M_B_RAS# 10 M_B_WE# 10 M_B_CAS# 10 M_CS#2 10 M_CS#3 10 M_CKE2 10 M_CKE3 10 M_CLK_DDR2 10 M_CLK_DDR#2 10 M_CLK_DDR3 10 M_CLK_DDR#3 10DM_B_DM[7..0] 10 M_B_DQS#[7..0] 10+3.3V_RUN 3 4 SA0_DIM1 RN1901 SRN10KJ-5-GPM_B_DQS[7..0] 10 M_B_A[15..0] 10 2 1 SA1_DIM110M_B_BS210 M_B_BS0 10 M_B_BS1 10 M_B_DQ[63..0]PM_EXTTS#1 9DY2 2C1902 SC2D2U10V3KX-1GP+V_DDR_REF1122C2C1923 SCD1U10V2KX-5GPC1924 SC2D2U10V3KX-1GP1 C1925 SCD1U10V2KX-5GPDYCSODIMM B DECOUPLING+1.5V_SUS11111112222222C1915 SCD1U10V2KX-5GP 2 1C1916 SCD1U10V2KX-5GP 2 1C1917 SCD1U10V2KX-5GP 2 1Layout Note: Place these Caps near SO-DIMMB.BC1918 SCD1U10V2KX-5GP212DYDYDY1C1905 SC10U10V5ZY-1GPC1906 SC10U6D3V5KX-1GPC1907 SC10U6D3V5KX-1GPC1908 SC10U6D3V5KX-1GPC1909 SC10U6D3V5KX-1GPC1910 SC10U6D3V5KX-1GPC1911 SC10U6D3V5KX-1GPC1912 SC10U6D3V5KX-1GPB9,18 DDR3_DRAMRST#Place these caps close to VTT1 and VTT2.H = 9.2mmDDR3-204P-43-GP111DY2DY2162.10017.N7122Note: SO-DIMMB SPD Address is 0xA4 SO-DIMMB TS Address is 0x34SO-DIMMB is placed farther from the Processor than SO-DIMMAAA&Core Design&Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. TitleDDR3-SODIMM2Size Date:5 4 3 2Document NumberRevDJ1 Calpella UMAThursday, April 22, 20101X0119 of 90Sheet54321SSID = PCHDDU2001D 37 PCH_VGA_BLEN 54 PCH_LCDVDD_EN 54 PCH_LBKLT_CTL 54 LDDC_CLK_PCH 54 LDDC_DATA_PCH LDDC_CLK_PCH LDDC_DATA_PCH LCTRL_CLK LCTRL_DATA LIBG R2003 TPAD14-GP RR2F-GP TP20014 OF 10T48 T47 Y48 AB48 Y45 AB46 V48 AP39 AP41 AT43 AT42 AV53 AV51 BB47 BA52 AY48 AV47 BB48 BA50 AY49 AV48 AP48 AP47 AY53 AT49 AU52 AT53 AY51 AT48 AU50 AT51L_BKLTEN L_VDD_EN L_BKLTCTL L_DDC_CLK L_DDC_DATA L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3SDVO_TVCLKINN SDVO_TVCLKINP SDVO_STALLN SDVO_STALLP SDVO_INTN SDVO_INTPBJ46 BG46 BJ48 BG48 BF45 BH452DY1 PCH_LCDVDD_ENPlace near PCH211LVDS_VBGSDVO_CTRLCLK SDVO_CTRLDATA DDPB_AUXN DDPB_AUXP DDPB_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3PT51 T53 BG44 BJ44 AU38 BD42 BC42 BJ42 BG42 BB40 BA40 AW38 BA38 Y49 AB49 BE44 BD44 AV40 BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 U50 U52 BC46 BD46 AT38 BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36100KR2J-1-GP54 PCH_LVDSA_TXC# 54 PCH_LVDSA_TXC 54 PCH_LVDSA_TX0# 54 PCH_LVDSA_TX1# 54 PCH_LVDSA_TX2# 54 PCH_LVDSA_TX0 54 PCH_LVDSA_TX1 54 PCH_LVDSA_TX2LVDS Digital Display InterfaceCImpedance:85 ohm+3.3V_RUNC4 3 2 1RN2002 SRN2K2J-4-GP5 6 7 8LCTRL_DATA LDDC_CLK_PCH LCTRL_CLK LDDC_DATA_PCHClose to ball &600mil55 PCH_CRT_BLUE 55 PCH_CRT_GREEN 55 PCH_CRT_REDBAA52 AB53 AD53Need Level ShiftRN2005 SRN150F-1-GP 55 PCH_CRT_DDCCLK 55 PCH_CRT_DDCDATA 55 PCH_CRT_HSYNC 55 PCH_CRT_VSYNCCRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTNV51 V53 Y53 Y51 AD48 AB51B1 R20012.5V Tolerance CRT_IREF 21KR2J-1-GP+3.3V_RUN IBEXPEAK-M-GP-NF1 2RN2003 SRN2K2J-1-GP4 3PCH_CRT_DDCCLK PCH_CRT_DDCDATACRTCRT SMBUS Close PCH4 3 2 15 6 7 8A&Core Design&AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. TitlePCH (LVDS/CRT/DDI)Size Date:5 4 3 2Document NumberRevDJ1 Calpella UMAThursday, April 22, 2010 Sheet1X0120 of 9054321RN2101 PCI_DEVSEL# PCI_IRDY# PCI_SERR# INT_PIRQC# +3.3V_RUN1 2 3 4 5SRN8K2J-2-GP-U10 9 8 7 6PCI_REQ2# INT_PIRQD# PCI_STOP# INT_PIRQA#+3.3V_RUNSSID = PCHU2001E5 OF 10RN2102DPCI_PERR# PCI_REQ0# PCI_REQ3# PCI_FRAME# +3.3V_RUN1 2 3 4 5SRN8K2J-2-GP-U10 9 8 7 6INT_PIRQB# PCI_PLOCK# PCI_REQ1# PCI_TRDY#+3.3V_RUN+3.3V_RUN +3.3V_RUN RN21031 2 3 4SRN10KJ-7GP8 7 6 5INT_PIRQF# INT_PIRQH# INT_PIRQG# INT_PIRQE# 9,37,70,76 PLT_RST#U21015 4B VCC Y1 2 3PCI_PLTRST#DYAGND74LVC1G08GW -1-GP11 R21042 0R0402-PADPCIH40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36 J50 G42 H47 G34INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# PCI_REQ0# PCI_REQ1# PCI_REQ2# PCI_REQ3#AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 C/BE0# C/BE1# C/BE2# C/BE3# PIRQA# PIRQB# PIRQC# PIRQD# REQ0# REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54 GNT0# GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55 PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 NV_DQS0 NV_DQS1 NV_DQ0/NV_IO0 NV_DQ1/NV_IO1 NV_DQ2/NV_IO2 NV_DQ3/NV_IO3 NV_DQ4/NV_IO4 NV_DQ5/NV_IO5 NV_DQ6/NV_IO6 NV_DQ7/NV_IO7 NV_DQ8/NV_IO8 NV_DQ9/NV_IO9 NV_DQ10/NV_IO10 NV_DQ11/NV_IO11 NV_DQ12/NV_IO12 NV_DQ13/NV_IO13 NV_DQ14/NV_IO14 NV_DQ15/NV_IO15 NV_ALE NV_CLE NV_RCOMP NV_RB# NV_WR#0_RE# NV_WR#1_RE# NV_WE#_CK0 NV_WE#_CK1 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P USBRBIAS#AY9 BD1 AP15 BD8 AV9 BG8 AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6 BD3 AY6 AU2 AV7 AY8 AY5 AV11 BF5NV_ALE NV_CLE NV_RCOMPDNVRAMDanbury Technology: Disabled when Low. Enable when High.1 1 1TP2100 TP2101 TP21022DYC2101 SC220P50V2KX-3GPUSB Pair Device USB0 (I/O Board) X USB2 USB3 X WLAN (I/O Board) X X X BLUETOOTH CARD READER CAMERA X XB CCG38 H51 B37 A44 F51 A46 B45 M53 F48 K45 F36 H53 B41 K53 A36 A48 K6 E44 E50 A42 H44 F46 C46 D49 D41 C48 M7 D5 N52 P53 P46 P51 P48BOOT BIOS Strap PCI_GNT#1 PCI_GNT#0 BOOT BIOS LocationTPAD14-GP TP2116 TPAD14-GP TP2117 TPAD14-GP TP21031 1 10 0 1 10 1 0 1LPC Reserved PCI SPI(Default)TPAD14-GP TP2108PCI_GNT0# PCI_GNT1# PCI_GNT2# PCI_GNT3# INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#1PCIRST# PCI_SERR# PCI_PERR# PCI_IRDY# PCI_DEVSEL# PCI_FRAME#PCIRST# SERR# PERR# IRDY# PAR DEVSEL# FRAME# PLOCK# STOP# TRDY# PME# PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4IBEXPEAK-M-GP-NFH18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 B25 D25 N16 J16 F16 L16 E14 G16 F12 T15USB_RBIAS_PNUSB_PN0 76 USB_PP0 76 USB_PN2 USB_PP2 USB_PN3 USB_PP3 63 63 63 630 1 2 3 4 5 6 7 8 9 10 11 12 13USB_PN5 76 USB_PP5 76USBUSB_PN9 73 USB_PP9 73 USB_PN10 32 USB_PP10 32 USB_PN11 54 USB_PP11 54BPCI_PLOCK# PCI_STOP# PCI_TRDY# TPAD14-GP TP2115USBRBIAS OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO141 2 RR2F-L1-GP1PCH_PME# PCI_PLTRST#70 23 37PCLK_FW H CLK_PCI_FB PCLK_KBCR2110 2DY22R2J-2-GP 1 2 R21081 22R2J-2-GP 2 R2111PCLK_FW H_R CLK_PCI_FB_R 1 PCLK_KBC_R 22R2J-2-GPUSB_OC#0_1 USB_OC#2_3 USB_OC#4_5 USB_OC#6_7 USB_OC#8_9 USB_OC#10_11 USB_OC#12_13 SMC_W AKE_SCI#_RUSB_OC#0_1 USB_OC#2_363 63A16 swap override Strap/Top-Block Swap Override jumper PCI_GNT#3 Low = A16 swap override/Top-Block Swap Override enabled High = DefaultRN2104 USB_OC#10_11 USB_OC#12_13 USB_OC#8_9 USB_OC#0_1 &Core Design& +3.3V_ALW USB_OC#4_5 USB_OC#6_7 USB_OC#2_3 SMC_W AKE_SCI#_R TitleAAR2109 PCI_GNT3#1DY2+3.3V_ALW1 2 3 4 5SRN10KJ-L3-GP10 9 8 7 6Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.4K7R2J-2-GPPCH (PCI/USB/NVRAM)Size Date:5 4 3 2Document NumberRevDJ1 Calpella UMAThursday, April 22, 2010 Sheet1X0121 of 9054321SSID = PCHU 8 8 8 8 8 8 8 8 8 8 8 8 8 8 +1.05V_VTT R2204 DMI_CTX_PRXN0 DMI_CTX_PRXN1 DMI_CTX_PRXN2 DMI_CTX_PRXN3 DMI_CTX_PRXP0 DMI_CTX_PRXP1 DMI_CTX_PRXP2 DMI_CTX_PRXP3 DMI_PTX_CRXN0 DMI_PTX_CRXN1 DMI_PTX_CRXN2 DMI_PTX_CRXN3 DMI_PTX_CRXP0 DMI_PTX_CRXP1 DMI_PTX_CRXP2 DMI_PTX_CRXP3 3 OF 10BC24 BJ22 AW20 BJ20 BD24 BG22 BA20 BG20 BE22 BF21 BD20 BE18 BD22 BH21 BC20 BD18 BH25DMI0RXN DMI1RXN DMI2RXN DMI3RXN DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP DMI_ZCOMP DMI_IRCOMPDFDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 BJ14 BF13 BH13 BJ12 BG14FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 FDI_INT8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8+3.3V_ALW RN2201 PM_RI# SUS_PW R_ACK PM_BATLOW #_R AC_PRESENT_EC1 2 3 4SRN10KJ-6-GP8 7 6 5DPCIE_W AKE#R220212 1KR2J-1-GPDMIFDIR2203 PCH_RSMRST#FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC11210KR2J-3-GP12DMI_IRCOMP_R +3.3V_RUNBF2549D9R2F-GPFDI_LSYNC11RJ-3-GP29CXDP_DBRESET#T6 M6R2207SYS_RESET# SYS_PWROK PWROK MEPWROK LAN_RST# DRAMPWROK RSMRST#WAKE# CLKRUN#/GPIO32J12 Y1PM_CLKRUN#PCIE_W AKE# 76CPM_CLKRUN#3737PM_PW ROK12 0R0402-PAD 2 10KR2J-3-GPPM_PW RGDB17 K5R2208 1System Power ManagementSUS_STAT#/GPIO61 SUSCLK/GPIO62 SLP_S5#/GPIO63 SLP_S4# SLP_S3# SLP_M# TP23 PMSYNCH SLP_LAN#/GPIO29P8 F3 E4 H7 P12 K8 N2 BJ10 F6PM_SUS_STAT# 1 TP2201TPAD14-GP PCH_SUSCLK PCH_SLP_S5# PM_SLP_S4#_R PM_SLP_S3#_R SIO_SLP_M#_R PM_SLP_DSW # H_PM_SYNC PM_SLP_LAN# RR2209 12 10KR2J-3-GPLAN_RST#1A10 D91 12 0R2J-2-GP 2 10R2J-2-GPPCH_SUSCLK_2102 PCH_SUSCLK_KBC39 379 PM_DRAM_PW RGD 37 PCH_RSMRST# 37 SUS_PW R_DN_ACK 9 PM_PW RBTN#_R 37 PM_PW RBTN# 37 AC_PRESENT_ECPM_DRAM_PW RGD R PM_RSMRST#_R 2 0R0402-PAD SUS_PW R_ACK 2 0R0402-PAD PM_PW RBTN#_R 0R0402-PAD R2216 AC_PRESENT 2 0R0402-PAD1TP2202 TPAD14-GP R121 1 2 1C16 M1 P5 P7 A6 F142 0R0402-PAD 2 0R0402-PADPM_SLP_S4# 37,50 PM_SLP_S3# 37,42,50,51SUS_PWR_DN_ACK/GPIO30 PWRBTN# ACPRESENT/GPIO31 BATLOW#/GPIO72 RI#IBEXPEAK-M-GP-NF11R22131TP2203TPAD14-GP1TP2204TPAD14-GP H_PM_SYNC 9BBPM_BATLOW #_R PM_RI#1TP2205TPAD14-GP+3.3V_RUNPM_CLKRUN# 12AOption to & Disable & clkrun. Pulling it down will keep the clks running.RJ-3-GP1DY2RJ-3-GP&Core Design&AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. TitlePCH (DM I/FDI/PM)Size Date:5 4 3 2Document NumberRevDJ1 Calpella UMAThursday, April 22, 2010 Sheet1X0122 of 9054321SSID = PCH+3.3V_ALW RJ-3-GP +3.3V_ALW1 2 3 4BG30 BJ30 BF29 BH29DPERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4 PERN5 PERP5 PETN5 PETP5 PERN6 PERP6 PETN6 PETP6 PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8 CLKOUT_PCIE0N CLKOUT_PCIE0P PCIECLKRQ0#/GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1#/GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P PCIECLKRQ2#/GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3#/GPIO25 CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4#/GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P PCIECLKRQ5#/GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P PEG_B_CLKRQ#/GPIO56IBEXPEAK-M-GP-NFSMBALERT#/GPIO11 SMBCLK SMBDATAB9 H14 C8 J14 C6 G8 M14 E10 G12 T13 T11 T9PCH_GPIO11 PCH_SMB_CLK PCH_SMB_DATA21+3.3V_ALWRN2301 SRN2K2J-2-GP1 2RN2302 SRN2K2J-1-GPU2001B2 OF 108 7 6 576 76 76 76 76 76 76 76PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 PCIE_RXN3 PCIE_RXP3 PCIE_TXN3 PCIE_TXP3C2305 SCD1U10V2KX-5GP 1 C2306 SCD1U10V2KX-5GP 12 2PCIE_C_TXN2 PCIE_C_TXP2AW30 BA30 BC30 BD30 AU30 AT30 AU32 AV32 BA32 BB32 BD32 BE32 BF33 BH33 BG32 BJ32 BA34 AW34 BC34 BD34 AT34 AU34 AU36 AV364 3R2302DWLAN SMBus LANSML0ALERT#/GPIO60 SML0CLK SML0DATA SML1ALERT#/GPIO74 SML1CLK/GPIO58TPM_ID1 SML0_CLK SML0_DATA2110KR2J-3-GP+3.3V_ALW SML0_CLK 9 SML0_DATA 9SML0_CLK SML0_DATAKBC_SCL1 KBC_SDA1PCH_SMB_CLK PCH_SMB_DATAC2303 SCD1U10V2KX-5GP 1 C2304 SCD1U10V2KX-5GP 12 2PCIE_C_TXN3 PCIE_C_TXP3R2303 LPD_SPI_INTR# KBC_SCL1 KBC_SDA1 CL_CLK2110KR2J-3-GP+3.3V_ALW KBC_SCL1 37 KBC_SDA1 37 +3.3V_RUNPCI-E*SML1DATA/GPIO75 CL_CLK1LinkController1TP2301TPAD14-GPRN2303CL_DATA1 CL_RST1#CL_DATA 1 TP2302TPAD14-GP CL_RST# 1 TP2303TPAD14-GP R2304 PEG_CLKREQ#2 13 4SRN2K2J-1-GPPEG_A_CLKRQ#/GPIO47 CLKOUT_PEG_A_N CLKOUT_PEG_A_PH1 AD43 AD45 AN4 AN2 AT1 AT32110KR2J-3-GP+3.3V_ALW PCH_SMB_DATAQ23016 51 2PCH_SMBDATA 7,18,19,76CCPCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3.3V_ALW. PCIECLKRQ{1,2} should have a 10K pull-up to +3.3_RUNBG34 BJ34 BG36 BJ36 AK48 AK47PEGCLKOUT_DMI_N CLKOUT_DMI_P CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P/CLKOUT_BCLK1_PCLK_EXP_N CLK_EXP_PCLK_EXP_N 9 CLK_EXP_P 943DMN66D0LDW -7-GP PCH_SMBCLK PCH_SMB_CLK 7,18,19,76From CLK BUFFERPCIE_CLK_RQ0#P9 AM43 AM45CLKIN_DMI_N CLKIN_DMI_P CLKIN_BCLK_N CLKIN_BCLK_P CLKIN_DOT_96N CLKIN_DOT_96P CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P REFCLK14IN CLKIN_PCILOOPBACK XTAL25_IN XTAL25_OUT XCLK_RCOMP CLKOUTFLEX0/GPIO64AW24 BA24 AP3 AP1 F18 E18 AH13 AH12 P41 J42 AH51 AH53 AF38 T45 P43 T42 N50CLKIN_DMI# CLKIN_DMI CLK_CPU_BCLK# CLK_CPU_BCLK DREFCLK# DREFCLK CLK_PCIE_SATA# CLK_PCIE_SATA CLK_PCH_14M CLK_PCI_FB XTAL25_IN XTAL25_OUT XCLK_RCOMP CLK_PCH_GPIO64CLKIN_DMI# 7 CLKIN_DMI 7 CLK_CPU_BCLK# 7 CLK_CPU_BCLK 7 DREFCLK# 7 DREFCLK 7 CLK_PCIE_SATA# 7 CLK_PCIE_SATA 7 CLK_PCH_14M CLK_PCI_FB 7 21PCIE_CLK_RQ1# CLK_PCIE_MINI1R# CLK_PCIE_MINI1R MINI1_CLK_REQ# CLK_PCIE_LAN1# CLK_PCIE_LAN1U4 AM47 AM48 N4 AH42 AH41 A8 AM51 AM53RN76 CLK_PCIE_MINI1# 76 CLK_PCIE_MINI1 76 MINI1_CLK_REQ# 76 CLK_PCIE_LAN# 76 CLK_PCIE_LANBRNP2R-PAD1 2RN4 3RNP2R-PAD1 2 24 3 1R2305PCIE_CLK_RQ3# 10KR2J-3-GPB1TP2305TPAD14-GP R 90D9R2F-1-GP +1.05V_VTT1 R23092 0R2J-2-GPPCIE_CLKRQ4#M9 AJ50 AJ521TP2304TPAD14-GPClock FlexPCIE_CLK_RQ5#H6 AK53 AK51CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67PEG_B_CLKRQ#P13CLK48_GPIOR2307 21 33R2J-2-GPCLK_48M_CARD32+3.3V_ALWARN2307+3.3V_RUN&Core Design&A8 7 6 51 2 3 4SRN10KJ-7GPPCIE_CLK_RQ0# PEG_B_CLKRQ# PCIE_CLKRQ4# PCIE_CLK_RQ5#1 24 3PCIE_CLK_RQ1# MINI1_CLK_REQ#Wistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. TitleRN2308 SRN10KJ-5-GPPCH (PCI-E/SMBUS/CLOCK/CL)Size Date:5 4 3 2Document NumberRevDJ1 Calpella UMAThursday, April 22, 2010 Sheet1X0123 of 9054321PCH_RTCX1 R2401+RTC_CELL RN SRN20KJ-GP-USSID = PCH1 2 4 3C2404 SC1U10V3KX-3GP G2401 GAP-OPEN12PCH_RTCX210MR2J-L-GP X2401INTVRMEN- Integrated SUS 1.1V VRM Enable High - Enable internal VRs2 11C2402 SC15P50V2JN-2-GP 2 14 1DU2001A C2403 SC15P50V2JN-2-GP PCH_RTCX1 PCH_RTCX2 PCH_RTCRST# SC1U10V3KX-3GP SRTCRST#1 OF 10LPC_LAD[0..3]23 2LPC_LAD[0..3]37,70DB13 D13 C14 D17 A16 A14RTCX1 RTCX2 RTCRST#82.X-32D768KHZ-40GPUFWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 FWH4/LFRAME#D33 B33 C32 A32 C34 A34 F34 AB9LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# 37,70RTCLPCSRTCRST# INTRUDER# INTVRMENC2401+RTC_CELL1 R04SM_INTRUDER# 1MR2J-1-GP PCH_INTVRMEN 2 330KR2F-L-GP2LDRQ0# LDRQ1#/GPIO23 SERIRQ1INT_SERIRQ37RN2402 30 PCH_AZ_CODEC_RST# 30 PCH_AZ_CODEC_BITCLK 30 PCH_AZ_CODEC_SYNC 30 PCH_SDOUT_CODEC21 2 3 48 7 6 5SRN33J-7-GP 30 ACZ_SPKRACZ_BIT_CLK ACZ_SYNC_R ACZ_SPKR ACZ_RST#_RA30 D29 P1 C30 G30 F30HDA_BCLK HDA_SYNC SPKR HDA_RST# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDO HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO13 SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA0RXN SATA0RXP SATA0TXN SATA0TXPAK7 AK6 AK11 AK9 AH6 AH5 AH9 AH8 AF11 AF9 AF7 AF6 AH3 AH1 AF3 AF1 AD9 AD8 AD6 AD5 AD3 AD1 AB3 AB1SATA_TXN0_C SATA_TXP0_CC06 12 SCD01U16V2KX-3GP 2 SCD01U16V2KX-3GPSATA_RXN0_C 59 SATA_RXP0_C 59 SATA_TXN0 59 SATA_TXP0 59 SATA_RXN1_C 59 SATA_RXP1_C 59 SATA_TXN1 59 SATA_TXP1 59HDD ODDC30 PCH_SDIN_CODECSATA_TXN1_C SATA_TXP1_CC08 12 SCD01U16V2KX-3GP 2 SCD01U16V2KX-3GPF32ACZ_SDATAOUT_RIHDACE32SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA3RXN SATA3RXP SATA3TXN SATA3TXPB29 H32 J3037 ME_UNLOCK#SATA+3.3V_RUNNO REBOOT STRAPNo Reboot Strap R23TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TP2404 TP2405 TP2406 TP2407 TP2408SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP1 1 1 1 1PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_RST#M3 K3 K1 J2 J4JTAG_TCK JTAG_TMS1 R2410DY2 ACZ_SPKR 1KR2J-1-GPLow = Default HDA_SPKR High = No RebootJTAGJTAG_TDI JTAG_TDO TRST#+1.05V_VTTSATAICOMPO SATAICOMPIAF16R2412AF15SATAICOMP12+3.3V_RUNSRN15J-2-GP 62 PCH_SPI_CLK 62 PCH_SPI_CS0# PCH_SPI_CLK PCH_SPI_CS0#37D4R2F-GP SPI_CLK_R SPI_CS#0_R+3.3V_RUNB2 1RN24033 4AV3 AY3SPI_CS0# SPI_CS1# SPI_MOSI SPI_MISOIBEXPEAK-M-GP-NFRJ-3-GP2 2RJ-3-GPBA2SPI_CLKBSATALED# SATA0GP/GPIO21 SATA1GP/GPIO19T3 Y9 V1SATA_DET#0_R SATA_DET#1_RSATA_LED#6662 PCH_SPI_DIPCH_SPI_DIAV1SPI1 R24112 INT_SERIRQ 10KR2J-3-GP62 PCH_SPI_DOPCH_SPI_DOR241512 15R2J-GPSPI_MOSI_RAY1A&Core Design&1 1AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. TitlePCH (SPI/RTC/LPC/SATA/IHDA)Size Date:5 4 3 2Document NumberRevDJ1 Calpella UMAThursday, April 22, 2010 Sheet1X0124 of 9054321+3.3V_RUNSSID = PCHU2001F 6 OF 10 S_GPIO1RJ-3-GP2Y3 C38 D37 J32 F10 K9 T7 AA2 F38 Y7 H10 AB12 V13 M11 V6 AB7 AB13 V3 P3 H3 F1 AB6S_GPIO 37DBMBUSY#/GPIO0 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 GPIO15 SATA4GP/GPIO16 TACH0/GPIO17SIO_EXT_SCI#SIO_EXT_SCI# PCH_GPIO6CLKOUT_PCIE6N CLKOUT_PCIE6PAH45 AH4637 SIO_EXT_W AKE# 37 SIO_EXT_SMI#SIO_EXT_W AKE#2C2501 SC47P50V2JN-3GP +3.3V_RUN1SIO_EXT_SMI# PCH_GPIO12 HOST_ALTERT#1 DGPU_HOLD_RST# PCH_GPIO17 PCH_GPIO22DYMISCCLKOUT_PCIE7N CLKOUT_PCIE7PAF48 AF47DA20GATEU2SIO_A20GATE 37CLKOUT_BCLK0_N/CLKOUT_PCIE8N CLKOUT_BCLK0_P/CLKOUT_PCIE8PAM3 AM1 BG10 T1 BE10 BD10BCLK_CPU_N BCLK_CPU_P H_PECI 9 SIO_RCIN# 379 9PCH_GPIO24 TPAD14-GP TP25072C2502 SC47P50V2JN-3GP R PCH_GPIO22 10KR2J-3-GPDYGPIO24 GPIO27 GPIO28 STP_PCI#/GPIO34GPIOSCLOCK/GPIO22PECI RCIN#1+1.05V_VTTPCH_GPIO28 STP_PCI# CLK_SATA_OE#CPU1PCH_GPIO27PROCPWRGD THRMTRIP#H_PW RGD 9,42 RN2505 PCH_THERMTRIP_R3 42 1SRN56J-4-GPH_THERMTRIP#9,37,42SATACLKREQ#/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 SLOAD/GPIO38 SDATAOUT0/GPIO39 PCIECLKRQ6#/GPIO45 PCIECLKRQ7#/GPIO46 SDATAOUT1/GPIO48 SATA5GP/GPIO49 GPIO57 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 BA22 AW22 BB22 AY45 AY46 AV43 AV45 AF13 M18 N18 AJ24 AK41 AK42 M32 N32 M30 N30 H12 AA23 AB45 AB38 AB42 AB41 T39 P6 C10INIT3_3V#B CRN25062PCH_GPIO36 RJ-3-GP PCH_GPIO37 PCH_GPIO38 PCH_GPIO39Placed Within 2& fromPCH1 2C4 3SIO_EXT_SCI# PCH_GPIO171SRN10KJ-5-GP+3.3V_ALW 9 DDR_RST_GATEPCH_GPIO45 DDR_RST_GATE PCH_GPIO481RJ-3-GP37 PCH_TEMP_ALERT#1R251820R0402-PADPCH_TEMP_ALERT#_C AA4 PCH_GPIO572F8PCH_GPIO28+3.3V_ALWTPAD14-GP PCH_GPIO57 HOST_ALTERT#1 PCH_GPIO45 DDR_RST_GATETP25101PCH_NCTF_11 R132 10KR2J-3-GP 2 1KR2J-1-GPB1 4 2 3 RN2509 SRN10KJ-5-GPPCH_GPIO24 PCH_GPIO12 SIO_EXT_SMI#2 R2514DY1 100KR2J-1-GP1 4 2 3 RN2501 SRN10KJ-5-GPTPAD14-GP TPAD14-GPTP2511 TP25121 1PCH_NCTF_2 PCH_NCTF_3+3.3V_RUN TPAD14-GP RN2503 SIO_EXT_W AKE# PCH_GPIO6 SRN10KJ-5-GP RN2507 DGPU_HOLD_RST# PCH_TEMP_ALERT#_C SRN10KJ-5-GPATP25091PCH_NCTF_4A4 A49 A5 A50 A52 A53 B2 B4 B52 B53 BE1 BE53 BF1 BF53 BH1 BH2 BH52 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D2 D53 E1 E53VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31IBEXPEAK-M-GP-NFTP11NCTFRSVDTP12 TP13 TP14 TP15 TP16 TP17 TP18 TP19 NC_1 NC_2 NC_3 NC_4 NC_5 INIT3_3V# TP241TP2506TPAD14-GP4 31 24 31 2&Core Design& PCH_GPIO37 PCH_GPIO48 RA1 12 10KR2J-3-GP 2 10KR2J-3-GPRN2502 RN2504 STP_PCI# PCH_GPIO39 SRN100KJ-6-GP+3.3V_RUNWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.PCH_GPIO38 PCH_GPIO36 SRN10KJ-5-GP4 31 24 31 2TitlePCH (GPIO/CPU)Size Date: Document Number RevDJ1 Calpella UMAThursday, April 22, 2010 Sheet1X0125 of 90543254321SSID = PCH+3.3V_RUN +1.05V_VTT1.524A1 1C2601 SC10U6D3V5KX-1GPDU2001G C2602 SC1U6D3V2KX-GPPOWERCRT7 OF 10DY2 2AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ3111VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCOREVCCADAC VCCADAC VSSA_DAC VSSA_DACC2605 SCD1U10V2KX-5GP1AE50 AE52+VCCA_DAC_1_2 C2603 SCD01U16V2KX-3GPC26061 L26022 HCB1608KF-181-GP+3.3V_CRT_LDODSC10U6D3V5MX-3GP22AF53 AF51VCC CORE21 L26032 DY HCB1608KF-181-GP+3.3V_RUN+3VS_VCCA_LVDVCCALVDS VSSA_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDSAH38 AH39 AP43 AP45 AT46 AT45C2616 1R 0R0603-PAD-1-GP2 DY 1 1C2619 SCD01U16V2KX-3GP1LVDSC26181+1.05V_VTTSCD1U10V2KX-5GP +1.8VS_VCCTX_LVDS SCD01U16V2KX-3GPR2611+1.8V_RUN2AK24TPAD14-GP TP2601VCCIO VCCAPLLEXP221+1.05VS_VCCAPLL_EXPBJ24 AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 AN30 AN312DY0R0805-PAD-2-GP C2617 SC10U6D3V5MX-3GP +3.3V_RUN X01VCC3_3 VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCC3_3 VCCVRM[1] VCCFDIPLLAB34 AB35 1 AD35 2HVCMOSVCC3_3 VCC3_3357mAC2607 SCD1U10V2KX-5GP+1.05V_VTTC3.208A1 1 1 1C2608 SC10U6D3V5KX-1GP C2609 SC1U10V3KX-3GP C2610 SC1U6D3V2KX-GP C2611 SC1U10V3KX-3GPC1C2612 SC1U6D3V2KX-GPDY2 2DY222+1.8V_RUNVCCVRMAT24 AT16 AU16 135mA+1.05V_VTT +1.05VS_VCC_DMIDMIVCCDMI VCCDMI1R SC1U10V3KX-3GP261mA 0R0402-PAD+3.3V_RUNPCI E*+3.3V_RUNC2614 SCD1U10V2KX-5GP357mABAN35 AT22 BJ18 AM23NAND / SPIVCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNANDAM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM152156mA1 2C2615 SCD1U10V2KX-5GP21+3.3V_RUNBVCCAFDI_VRM +1.05V_VTT TPAD14-GP TP26021 VCCME3_3 VCCME3_3 VCCME3_3 VCCME3_3 AM8 AM9 AP11 AP9 11VCCAFDIPLL85mAPCH_VCCME3_3 C2622 SCD1U10V2KX-5GPR2-PADFDIVCCIO22IBEXPEAK-M-GP-NF3.3V CRT LDO+5V_RUN UV_CRT_LDO3 2 1 1+1.8V_RUN VCCAFDI_VRM R SC1U10V2KX-1GPVIN GND ENDYVOUT NC#54 5 1DYRT9198-33PBG-GPDY2C2620 SC1U6D3V2KX-GP2120R0402-PADSecond 74.09091.H3FA&Core Design&AWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. TitlePCH (POWER1)Size Date:5 4 3 2Document NumberRevDJ1 Calpella UMAW ednesday, April 21, 2010 Sheet1X0126 of 9054321U2001J TPAD14-GP TP2515POWERSSID = PCH10 OF 10 +1.05V_VTT1VCCACLKAP51 AP53 AF23 AF24VCCACLK VCCACLK VCCLAN VCCLAN DCPSUSBYP VCCME VCCME VCCME VCCME VCCME VCCMEVCCIO VCCIO VCCIO VCCIO VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCIO V5REF_SUSV24 V26 Y24 Y26 V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 U23 V23 F241 2C2706DY SC1U10V2KX-1GP+3.3V_ALWDDDCPSUSBYP C2707 SCD1U10V2KX-5GP1 2Y20 AD3821C2703 SCD1U10V2KX-5GP+1.05V_VTTAD41 AF431.998A1 1C2704 SC10U6D3V5KX-1GP C2705 SC10U6D3V5MX-3GP1AF41C2708DY2 2AF42 2 V39 V41 V42 Y39C2710USBAD39VCCME VCCME VCCME VCCME VCCMEClock and Miscellaneous1+1.05V_VTT12SC1U6D3V2KX-GP SC1U6D3V2KX-GPVCCME+3.3V_ALW+3.3V_ALW12C2709 SCD1U10V2KX-5GP +1.05V_VTT+3.3V_RUN D2701 CH751H-40PT-GP111 L2702C2 0R0805-PAD+1.05VS_VCCA_A_DPL C2713 SCD1U10V2KX-5GP C2711 SC1U6D3V2KX-GPDY2+VCCRTCEXTY42+5V_ALW +5VALW _PCH_VCC5REFSUS2D2702 CH751H-40PT-GPCY411 1R SC1U10V2KX-1GP22C2734 DY SC10U6D3V5MX-3GPV9DCPRTC12 100R2F-L1-GP-U1+5V_RUN111 L27032 0R0805-PAD22C2735 DY SC10U6D3V5MX-3GPC2714 SC1U6D3V2KX-GP72mA +1.05VS_VCCA_A_DPL 73mA +1.05VS_VCCA_B_DPLVCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3+3.3V_RUNM36 1 N36 P36 U35 1 AD13 2C2716 SCD1U10V2KX-5GP CV_RUNBD51 BD53 AH23 AJ35 AH35VCCADPLLB VCCADPLLB VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO DCPSST+1.05V_VTT2SCD1U10V2KX-5GPAF34 1 1C2719 SC1U6D3V2KX-GP C2720 SC1U6D3V2KX-GPC2718 SC1U6D3V2KX-GP1AH34 AF32 V12VCCSATAPLL VCCSATAPLLAK3 AK122B+VCCSST C2724 SCD1U10V2KX-5GP2VCCSATAPLL1TP2514TPAD14-GP2BB51 BB53VCC3_3J38 L38C2715 SC1U10V2KX-1GPVCCADPLLA VCCADPLLA1+1.05VS_VCCA_B_DPLVCCVRMPCI/GPIO/LPC2AU24V5REFK49+5VS_PCH_VCC5REF2+1.8V_RUN1R27022 100R2F-L1-GP-UPCI/GPIO/LPC+3.3V_ALW163mA1 2+3.3V_RUN C2727 SCD1U10V2KX-5GPVCCSUS3_3 VCCSUS3_3 VCCSUS3_3SATAU19 U20 U22VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCME VCCME VCCME VCCME VCCSUSHDAAH19 AD20 AF22 AD19 AF20 AF19 AH20 AB19 AB20 AB22 AD22 AA34 Y34 Y35 AA35&Core Design&AV15 1 V16 2 Y16VCC3_3 VCC3_3 VCC3_3+1.05V_VTT1mA1C2728 SC4D7U10V5KX-4GPA+1.05V_VTTAT18 1C2730C2729AU18 2V_CPU_IO22CPUV_CPU_IO1RTC+RTC_CELLHDAA122mAVCCRTCIBEXPEAK-M-GP-NFL306mA1 2R270712 0R0402-PAD+3.3V_ALW2C2723 SCD1U10V2KX-5GP1+1.05V_VTTB+1.05VALW _INT_VCCSUSY22DCPSUS VCCIO21AH22+1.8V_RUN12P18VCCSUS3_3VCCVRMAT20C2725 SC1U6D3V2KX-GP1C2732122C2726 SCD1U10V2KX-5GPSCD1U10V2KX-5GP SCD1U10V2KX-5GPSCD1U10V2KX-5GP SCD1U10V2KX-5GPWistron Corporation21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. TitleC2733C2731 SC1U10V2KX-1GP+3VS_+1.5VS_HDA_IO Size Date: Document Number Friday, April 16, 2010PCH (POWER2)Sheet1RevDJ1 Calpella UMA27 of 903 2X015454321SSID = PCHAY7 B11 B15 B19 B23 B31 B35 B39 B43 B47 B7 BG12 BB12 BB16 BB20 BB24 BB30 BB34 BB38 BB42 BB49 BB5 BC10 BC14 BC18 BC2 BC22 BC32 BC36 BC40 BC44 BC52 BH9 BD48 BD49 BD5 BE12 BE16 BE20 BE24 BE30 BE34 BE38 BE42 BE46 BE48 BE50 BE6 BE8 BF3 BF49 BF51 BG18 BG24 BG4 BG50 BH11 BH15 BH19 BH23 BH31 BH35 BH39 BH43 BH47 BH7 C12 C50 D51 E12 E16}