ADC14C065 (NSC) PDF技术资料下载
ADC14C065 供应信息 IC Datasheet 数据表 (1/17 页)
按型号查询：
14位， 65/80/95/105 MSPS A / D转换器
[14-Bit, 65/80/95/105 MSPS A/D Converter]
&&ADC14C065PDF文件：
14位， 65/80/95/105 MSPS A / D转换器[14-Bit, 65/80/95/105 MSPS A/D Converter]
文件大小：&&615 KPDF页数：
&&17 页联系供应商：&& 品牌Logo:
&&&&NSC [ NATIONAL SEMICONDUCTOR ]
ADC14C065/ADC14C080/ADC14C095/ADC14C105 14-Bit, 65/80/95/105 MSPS A/D ConverterADVANCE INFORMATIONSeptember 2006ADC14C065/ADC14C080/ADC14C095/ADC14C10514-Bit, 65/80/95/105 MSPS A/D ConverterGeneral DescriptionNOTE: This is Advance Information for products cur-rently in development. ALL specifications are designtargets and are subject to change.The ADC14C065, ADC14C080, ADC14C095, andADC14105 are high-performance CMOS analog-to-digitalconverters capable of converting analog input signals into14-bit digital words at rates up to 65/80/95/105 MegaSamples Per Second (MSPS) respectively. These convert-ers use a differential, pipelined architecture with digital errorcorrection and an on-chip sample-and-hold circuit to mini-mize power consumption and the external component count,while providing excellent dynamic performance. A uniquesample-and-hold stage yields a full-power bandwidth of 1GHz. The ADC14C065/080/095/105 may be operated from asingle +3.3V power supply and consumes low power.A separate +2.5V supply may be used for the digital outputinterface which allows lower power operation with reducednoise. A power-down feature reduces the power consump-tion to very low levels while still allowing fast wake-up time tofull operation. The differential inputs provide a 2V full scaledifferential input swing. A stable 1.2V internal voltage refer-ence is provided, or the ADC14C065/080/095/105 can beoperated with an external 1.2V reference. Output data for-mat (offset binary versus 2’s complement) and duty cyclestabilizer are pin-selectable. The duty cycle stabilizer main-tains performance over a wide range of clock duty cycles.The ADC14C065/080/095/105 is available in a 32-lead LLPpackage and operates over the industrial temperature rangeof -40?C to +85?C.Featuresnnnnnnnnnn1 GHz Full Power BandwidthInternal sample-and-hold circuitLow power consumptionInternal precision referenceData Ready output clockClock Duty Cycle StabilizerSingle +3.3V supply operationPower-down modeOffset binary or 2’s complement output data format32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch)Key SpecificationsnnnnnnnFor ADC14C105ResolutionConversion RateSNR (fIN= 240 MHz)SFDR (fIN= 240 MHz)Full Power BandwidthPower Consumption14 Bits105 MSPS72 dBFS (typ)83 dBFS (typ)1 GHz (typ)400 mW (typ)ApplicationsnnnnnHigh IF Sampling ReceiversWireless Base Station ReceiversTest and Measurement EquipmentCommunications InstrumentationPortable InstrumentationConnection Diagram(C) 2006 National Semiconductor CorporationDS202098400万器件资料库等您来搜！
> ADC-30720
器件名称: ADC-30720
功能描述: 8-Bit, 20MSPS CMOS Flash A/D
文件大小: 109.89KB&&&&共4页
下　　载: &&& &
ADC-30634/ADC-30720
8-Bit, 20MSPS CMOS Flash A/D (ADC-208 Compatible)
8-bit ash A/D converter 20MHz sampling rate 10MHz full-power bandwidth Sample-hold not required Low power CMOS +5Vdc operation 1.2 Micron CMOS 8-Bit latched outputs Surface-mount version No missing codes PIN
1 2 3 4 5 6 7 8 9 10 11 12
INPUT/OUTPUT CONNECTIONS
VDD CLOCK INPUT –REFERENCE ANA/DIG GND (VSS) ANALOG INPUT REF MIDPOINT ANALOG INPUT ANA/DIG GND (VSS) +REFERENCE VDD N.C. N.C.
24 23 22 21 20 19 18 17 16 15 14 13
BIT 8 (LSB) BIT 7 BIT 6 BIT 5 REF 1/4 FS VDD REF 3/4 FS BIT 4 BIT 3 BIT 2 BIT 1 (MSB) N.C.
GENERAL DESCRIPTION
The ADC-30634 and ADC-30720 utilizes an advanced VLSI 1.2 micron CMOS in providing 20MHz sampling rates at 8-bits. The exibility of the design architecture and process delivers latch-up free operation without external components and operation over the full military range. The ADC-30634 and ADC-30720 are mechanically and electrically equivalent to the ADC-208LM and ADC208MM-QL, respectively, with the exception of the OVERFLOW (pin 13) and ENABLE (pins 11 and 12) functions. These functions are not offered on the ADC-30634 and ADC30720.
ANALOG INPUT
CLOCK GENERATOR
R2 +REFERENCE
1 R2 MIDPOINT REFERENCE
D G Q 256 to 7 ENCODER D G Q
R2 D G D G R R2 Q D G Q Q
相关电子器件
器件名 功能描述 生产厂商
8-Bit, 20MSPS CMOS Flash A/D
《电子产品世界》杂志社 版权所有 北京东晓国际技术信息咨询有限公司
Copyright (C)2002 ELECTRONIC ENGINEERING & PRODUCT WORLD. All rights reserved.
京ICP备号-2ADC14V155 具有 LVDS 输出的 14 位、155 MSPS、1.1 GHz 带宽 A/D 转换器 | 德州仪器
10MSPS), 数据转换器, 数据转换器, semiconductors, analog" />
10MSPS)" />
(正在供货)
具有 LVDS 输出的 14 位、155 MSPS、1.1 GHz 带宽 A/D 转换器
&(英文內容)
In English
日本語表示
相关终端应用
The ADC14V155 is a high-performance CMOS analog-to-digital converter with LVDS outputs.
It is capable of converting analog input signals into 14-Bit digital words at rates up to 155 Mega
Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data rate) this allows both
edges of the output clock to be utilized while achieving a smaller package size. This converter
uses a differential, pipelined architecture with digital error correction and an on-chip
sample-and-hold circuit to minimize power consumption and the external component count, while
providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power
bandwidth of 1.1 GHz. The ADC14V155 operates from dual +3.3V and +1.8V power supplies and consumes
951 mW of power at 155 MSPS.
The separate +1.8V supply for the digital output interface allows lower power operation
with reduced noise. A power-down feature reduces the power consumption to 15 mW while still
allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes
50 mW of power and has a faster wake-up time.
The differential inputs provide a full scale differential input swing equal to 2 times
the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14V155 can
be operated with an external reference.
Clock mode (differential versus single-ended) and output data format (offset binary
versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a
wide range of input clock duty cycles.
The ADC14V155 is pin-compatible with the ADC12V170. It is available in a 48-lead WQFN
package and operates over the industrial temperature range of &40&C to +85&C.
1.1 GHz Full Power
Bandwidth Internal Sample-and-Hold Circuit Low Power
Consumption Internal Precision 1.0V Reference Single-Ended
or Differential Clock Modes Clock Duty Cycle
Stabilizer Dual +3.3V and +1.8V Supply Operation Power-Down
and Sleep Modes Offset Binary or 2's Complement Output Data
Format Dual Data Rate (DDR) LVDS Outputs Pin-Compatible:
ADC12V170 48-Pin WQFN Package, (7x7x0.8mm, 0.5mm
Pin-Pitch)
Key Specifications Resolution 14
Bits Conversion Rate 155 MSPS SNR
(fIN = 70 MHz) 71.7 dBFS (typ) SFDR
(fIN = 70 MHz) 86.9 dBFS (typ) ENOB
(fIN = 70 MHz) 11.5 bits (typ) Full Power Bandwidth 1.1
GHz (typ) Power Consumption 951 mW
All trademarks are the property of their respective owners.
查看更多内容
Resolution
Sample Rate
# Input Channels
Power Consumption
Input Range
Operating Temperature Range
Analog Input BW
Input Buffer
Package Group
Package Size: mm2:W x L (PKG)
Architecture
Reference Mode
DDR LVDS Parallel LVDS&
Parallel CMOS&
-40 to 85&
-40 to 85&
48WQFN: 49 mm2: 7 x 7(WQFN)&
48WQFN: 49 mm2: 7 x 7(WQFN)&
特色工具和软件
(计算工具)
(应用软件与框架)
(计算工具)}